Saturday June 30 2018 |
Time | Replies | Subject |
11:56PM |
1 |
Determine reason for failure at -O1 |
6:37PM |
0 |
Determine reason for failure at -O1 |
2:57PM |
2 |
Using BuildMI to insert Intel MPX instruction BNDCU failed |
7:49AM |
4 |
Determine reason for failure at -O1 |
|
Friday June 29 2018 |
Time | Replies | Subject |
10:59PM |
0 |
Cleaning up ‘br i1 false’ cases in CodeGenPrepare |
10:34PM |
0 |
[RFC][VECLIB] how should we legalize VECLIB calls? |
10:25PM |
2 |
Cleaning up ‘br i1 false’ cases in CodeGenPrepare |
8:15PM |
2 |
[RFC][VECLIB] how should we legalize VECLIB calls? |
7:20PM |
0 |
Cleaning up ‘br i1 false’ cases in CodeGenPrepare |
5:59PM |
2 |
2018 LLVM Dev Mtg - Call for Papers (Deadline July 30) |
3:41PM |
1 |
Converting Value* to GenericValue for runFunction? |
1:18PM |
1 |
[SelectionDAG] lowering shifts to parts |
9:59AM |
0 |
London LLVM Social Thursday July 19 |
7:44AM |
0 |
[LNT] Tests for web UI/javascript? |
6:36AM |
0 |
[RFC][VECLIB] how should we legalize VECLIB calls? |
4:44AM |
2 |
Cleaning up ‘br i1 false’ cases in CodeGenPrepare |
4:01AM |
1 |
llvm-link is creating 32 and 64-bit versions of a struct |
2:11AM |
2 |
[RFC][VECLIB] how should we legalize VECLIB calls? |
|
Thursday June 28 2018 |
Time | Replies | Subject |
11:32PM |
0 |
XRay feature – pid reporting |
10:47PM |
0 |
can debug info for coroutines be improved? |
9:30PM |
2 |
[LNT] Tests for web UI/javascript? |
9:27PM |
0 |
Since MCJIT I can't get libm functions to work |
9:18PM |
2 |
XRay feature – pid reporting |
8:49PM |
2 |
Since MCJIT I can't get libm functions to work |
8:38PM |
0 |
Since MCJIT I can't get libm functions to work |
7:40PM |
3 |
Since MCJIT I can't get libm functions to work |
5:49PM |
0 |
lld link error building llvm-shlib for mingw-w64 |
5:35PM |
0 |
[LNT] Tests for web UI/javascript? |
4:48PM |
2 |
[LNT] Tests for web UI/javascript? |
3:27PM |
1 |
One more Question about handling pointer with restrict keyword on Alias Analysis |
3:23PM |
0 |
RFC: [SLP] Vectorize bit-parallel operations using general purpose registers. |
1:07PM |
0 |
Distinguish between ARM and Thumb |
12:39PM |
1 |
Branch probabilities for invokes |
12:32PM |
2 |
Distinguish between ARM and Thumb |
3:29AM |
0 |
XRay feature – pid reporting |
1:23AM |
0 |
LLVM Scheduler Target Description |
|
Wednesday June 27 2018 |
Time | Replies | Subject |
11:14PM |
1 |
libFuzzer signal handling tests |
9:27PM |
0 |
[X86_64] [Q] Object code generated to access global variables |
8:36PM |
0 |
Specify attributes for Mach-O section |
6:04PM |
1 |
[Green Dragon] System upgrade and reboot today at 12:00PDT |
5:41PM |
2 |
can debug info for coroutines be improved? |
5:18PM |
1 |
[lldb-dev] RFC: libtrace |
1:11PM |
0 |
[lldb-dev] RFC: libtrace |
10:27AM |
1 |
RFC: clang option to tolerate Windows-style #include paths? |
10:16AM |
0 |
Add LLDB Repository to Phabricator |
7:56AM |
2 |
[lldb-dev] RFC: libtrace |
7:32AM |
0 |
accessing subwords in memory |
6:29AM |
3 |
LLVM 6.0.1-final has been tagged |
12:49AM |
1 |
MachineFunction Instructions Pass using Segment Registers |
12:14AM |
0 |
[lldb-dev] RFC: libtrace |
|
Tuesday June 26 2018 |
Time | Replies | Subject |
11:37PM |
0 |
XRay TID mismatch when forking |
11:31PM |
0 |
XRay feature – pid reporting |
10:45PM |
1 |
question about loop unrolling |
9:00PM |
0 |
[lldb-dev] RFC: libtrace |
8:49PM |
0 |
RFC: libtrace |
8:38PM |
4 |
RFC: libtrace |
8:37PM |
0 |
MachineFunction Instructions Pass using Segment Registers |
8:28PM |
0 |
RFC: libtrace |
8:13PM |
2 |
MachineFunction Instructions Pass using Segment Registers |
8:09PM |
4 |
[lldb-dev] RFC: libtrace |
7:59PM |
0 |
[lldb-dev] RFC: libtrace |
7:57PM |
0 |
MachineFunction Instructions Pass using Segment Registers |
7:48PM |
2 |
[lldb-dev] RFC: libtrace |
7:26PM |
0 |
[lldb-dev] RFC: libtrace |
7:06PM |
3 |
accessing subwords in memory |
6:58PM |
4 |
RFC: libtrace |
5:51PM |
0 |
[Green Dragon] Green Dragon restart tomorrow Wednesday June 27 @ 12:00PDT |
4:30PM |
1 |
LLVMSymbolizer can't find DIA library |
4:20PM |
0 |
How to force an unused function declaration in clang |
3:58PM |
2 |
How to force an unused function declaration in clang |
3:24PM |
0 |
How to force an unused function declaration in clang |
3:21PM |
2 |
How to force an unused function declaration in clang |
2:43PM |
0 |
Instruction boundaries |
2:14PM |
2 |
Instruction boundaries |
1:39PM |
1 |
Addition to LLVM Users list |
1:38PM |
0 |
Instruction boundaries |
1:29PM |
0 |
How to force an unused function declaration in clang |
1:08PM |
2 |
Instruction boundaries |
9:36AM |
1 |
JIT and static constructors/destructors. |
5:44AM |
0 |
Instruction boundaries |
3:31AM |
2 |
Instruction boundaries |
3:18AM |
0 |
[Job Ad] Red Hat is hiring an LLVM Software Engineer |
2:31AM |
1 |
runStaticConstructorsDestructors() causes crash on exit |
12:48AM |
2 |
How to force an unused function declaration in clang |
|
Monday June 25 2018 |
Time | Replies | Subject |
9:20PM |
0 |
How to include a opt pass in clang driver |
9:07PM |
4 |
XRay feature – pid reporting |
9:03PM |
2 |
How to include a opt pass in clang driver |
8:57PM |
0 |
How to include a opt pass in clang driver |
8:38PM |
2 |
How to include a opt pass in clang driver |
6:48PM |
0 |
Build files |
6:38PM |
0 |
Instruction boundaries |
5:18PM |
0 |
Simplifying and matching sign-extended expressions |
4:21PM |
0 |
runStaticConstructorsDestructors() causes crash on exit |
4:21PM |
0 |
LLVM buildmaster will be restarted tonight |
3:36PM |
2 |
Instruction boundaries |
2:28PM |
2 |
runStaticConstructorsDestructors() causes crash on exit |
2:00PM |
1 |
XRay feature – fdr log flushing |
1:17PM |
0 |
Building LLVM 6.0.1-rc3 on MacOS with static libc++ and no references to /usr/lib/libc++.1.dylib? |
10:54AM |
0 |
Is that LLVM Language Reference Manual's bug? |
10:05AM |
2 |
Is that LLVM Language Reference Manual's bug? |
9:55AM |
0 |
LLVM Weekly - #234, June 25th 2018 |
|
Sunday June 24 2018 |
Time | Replies | Subject |
9:19PM |
0 |
Vectorization in multiple threads |
3:32AM |
2 |
MachineFunction Instructions Pass using Segment Registers |
2:55AM |
0 |
MachineFunction Instructions Pass using Segment Registers |
12:45AM |
2 |
MachineFunction Instructions Pass using Segment Registers |
12:36AM |
0 |
MachineFunction Instructions Pass using Segment Registers |
12:28AM |
2 |
MachineFunction Instructions Pass using Segment Registers |
|
Saturday June 23 2018 |
Time | Replies | Subject |
11:17PM |
0 |
RFC: Should SmallVectors be smaller? |
6:48PM |
2 |
RFC: Should SmallVectors be smaller? |
6:35PM |
0 |
RFC: Should SmallVectors be smaller? |
6:27PM |
4 |
RFC: Should SmallVectors be smaller? |
5:14PM |
0 |
RFC: Should SmallVectors be smaller? |
4:11PM |
2 |
RFC: Should SmallVectors be smaller? |
11:10AM |
2 |
Build files |
|
Friday June 22 2018 |
Time | Replies | Subject |
10:18PM |
0 |
RFC: Should SmallVectors be smaller? |
4:16AM |
3 |
RFC: Should SmallVectors be smaller? |
2:30AM |
1 |
RFC: Should SmallVectors be smaller? |
2:01AM |
0 |
RFC: Should SmallVectors be smaller? |
1:38AM |
0 |
RFC: Should SmallVectors be smaller? |
|
Thursday June 21 2018 |
Time | Replies | Subject |
9:27PM |
0 |
Finding Reduction Variables in a Loop |
7:49PM |
0 |
NVPTX - Reordering load instructions |
7:32PM |
2 |
NVPTX - Reordering load instructions |
6:50PM |
0 |
[RFC] Removing debug locations from ConstantSDNodes |
6:25PM |
0 |
Target hardware loop instruction via intrinsics |
6:07PM |
3 |
Target hardware loop instruction via intrinsics |
5:48PM |
0 |
NVPTX - Reordering load instructions |
5:18PM |
2 |
NVPTX - Reordering load instructions |
4:57PM |
0 |
[RFC] Removing debug locations from ConstantSDNodes |
4:52PM |
4 |
RFC: Should SmallVectors be smaller? |
4:28PM |
2 |
[RFC] Removing debug locations from ConstantSDNodes |
3:18PM |
0 |
Bug-closing protocol |
1:07PM |
0 |
[RFC] Removing debug locations from ConstantSDNodes |
12:56PM |
2 |
Bug-closing protocol |
10:28AM |
0 |
runStaticConstructorsDestructors() causes crash on exit |
8:38AM |
0 |
add new instruction format |
7:27AM |
2 |
runStaticConstructorsDestructors() causes crash on exit |
7:17AM |
0 |
PostRAScheduler |
1:06AM |
2 |
add new instruction format |
|
Wednesday June 20 2018 |
Time | Replies | Subject |
11:31PM |
5 |
[RFC] Removing debug locations from ConstantSDNodes |
10:11PM |
0 |
Bug-closing protocol |
9:08PM |
0 |
runStaticConstructorsDestructors() causes crash on exit |
7:20PM |
1 |
Using lnt to run SPEC tests: possible or not? |
7:02PM |
0 |
adding 2 new functions to the AliasAnalysis interface |
6:52PM |
0 |
Triple to emit x86_64-apple-macosx as elf |
6:09PM |
0 |
[RFC] Removing debug locations from ConstantSDNodes |
5:47PM |
2 |
[RFC] Removing debug locations from ConstantSDNodes |
3:51PM |
2 |
PostRAScheduler |
2:10PM |
1 |
FW: RFC: Atomic LL/SC loops in LLVM revisited |
2:09PM |
1 |
Node deletion during DAG Combination ? |
9:31AM |
2 |
adding 2 new functions to the AliasAnalysis interface |
9:12AM |
0 |
Node deletion during DAG Combination ? |
8:18AM |
2 |
Node deletion during DAG Combination ? |
7:02AM |
0 |
Using lnt to run SPEC tests: possible or not? |
2:20AM |
1 |
[RFC] Removing debug locations from ConstantSDNodes |
1:36AM |
0 |
[RFC] Removing debug locations from ConstantSDNodes |
12:51AM |
0 |
Bug-closing protocol |
12:46AM |
4 |
[RFC] Removing debug locations from ConstantSDNodes |
|
Tuesday June 19 2018 |
Time | Replies | Subject |
9:53PM |
2 |
Using lnt to run SPEC tests: possible or not? |
8:51PM |
1 |
[RFC] Formalizing FileCheck Features |
8:18PM |
1 |
Naming clash: -DCLS=n and CLS in code |
8:14PM |
0 |
Naming clash: -DCLS=n and CLS in code |
8:09PM |
0 |
null register def operands |
7:49PM |
3 |
Naming clash: -DCLS=n and CLS in code |
7:46PM |
0 |
Naming clash: -DCLS=n and CLS in code |
7:41PM |
0 |
Naming clash: -DCLS=n and CLS in code |
7:33PM |
2 |
Naming clash: -DCLS=n and CLS in code |
7:22PM |
0 |
Naming clash: -DCLS=n and CLS in code |
7:12PM |
6 |
Naming clash: -DCLS=n and CLS in code |
6:54PM |
0 |
Naming clash: -DCLS=n and CLS in code |
6:48PM |
2 |
Naming clash: -DCLS=n and CLS in code |
5:55PM |
0 |
Naming clash: -DCLS=n and CLS in code |
5:22PM |
2 |
Naming clash: -DCLS=n and CLS in code |
3:54PM |
2 |
runStaticConstructorsDestructors() causes crash on exit |
11:43AM |
0 |
About 161 warnings by gcc/g++ when building llvm & clang/clang++ with it |
9:33AM |
1 |
Question about Alias Analysis with restrict keyword |
5:17AM |
1 |
2018 LLVM Dev Mtg - Program committee volunteers needed |
3:17AM |
0 |
LLVM Sydney Users and Developers Meetup (#2) |
|
Monday June 18 2018 |
Time | Replies | Subject |
11:57PM |
0 |
Buildbot numbers for the week of 6/10/2018 - 6/16/2018 |
11:57PM |
0 |
Buildbot numbers for the week of 6/3/2018 - 6/9/2018 |
11:57PM |
0 |
Buildbot numbers for the week of 5/27/2018 - 6/2/2018 |
10:20PM |
5 |
Bug-closing protocol |
10:17PM |
0 |
Question about Alias Analysis with restrict keyword |
10:01PM |
1 |
[cfe-dev] LLVM Bay Area Social July poll |
8:12PM |
0 |
LLVM Weekly - #233, June 18th 2018 |
4:57PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
4:54PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
4:17PM |
3 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
3:16PM |
2 |
Question about Alias Analysis with restrict keyword |
12:33PM |
0 |
[cfe-dev] 6.0.1-rc3 has been tagged |
8:58AM |
1 |
[RFC] RISC-V backend |
2:06AM |
1 |
Store Instruction pattern match |
|
Sunday June 17 2018 |
Time | Replies | Subject |
11:53AM |
0 |
RFC: Atomic LL/SC loops in LLVM revisited |
9:08AM |
0 |
LLVM force vector width on individual loops |
7:42AM |
0 |
status of msp430? |
1:46AM |
2 |
status of msp430? |
|
Saturday June 16 2018 |
Time | Replies | Subject |
9:57PM |
0 |
Codeowner for MIPS |
4:15PM |
0 |
Register Rematerialization |
|
Friday June 15 2018 |
Time | Replies | Subject |
11:36PM |
1 |
Generate MASM output from llc? |
10:03PM |
0 |
RFC: Atomic LL/SC loops in LLVM revisited |
10:00PM |
1 |
Math functions for CUDA patch |
8:51PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
8:48PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
8:40PM |
2 |
[WebAssembly] lld dynamic loader |
7:13PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:59PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
5:57PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
5:49PM |
0 |
Commit module to Git after each Pass |
5:40PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
5:14PM |
0 |
Strange Machineinstr |
5:09PM |
2 |
Strange Machineinstr |
4:58PM |
0 |
Strange Machineinstr |
4:51PM |
2 |
Commit module to Git after each Pass |
4:45PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
4:43PM |
3 |
Strange Machineinstr |
4:33PM |
0 |
Strange Machineinstr |
4:28PM |
2 |
Strange Machineinstr |
4:23PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
4:19PM |
2 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
3:21PM |
0 |
RFC: Atomic LL/SC loops in LLVM revisited |
3:07PM |
1 |
[RISCV] Hard float ABI and testing |
2:42PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
1:11PM |
0 |
LLVM assembly language |
11:30AM |
3 |
Codeowner for MIPS |
11:28AM |
2 |
RFC: Atomic LL/SC loops in LLVM revisited |
10:34AM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
9:23AM |
0 |
runStaticConstructorsDestructors() causes crash on exit |
7:35AM |
0 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
7:16AM |
0 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
5:12AM |
7 |
6.0.1-rc3 has been tagged |
12:47AM |
0 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
12:34AM |
0 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
12:10AM |
0 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
|
Thursday June 14 2018 |
Time | Replies | Subject |
11:10PM |
0 |
2018 LLVM Developers' Meeting - Bay Area, October 17-18 |
10:16PM |
2 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
9:38PM |
0 |
[cfe-dev] LLVM Bay Area Social July poll |
9:35PM |
2 |
LLVM Bay Area Social July poll |
8:48PM |
0 |
Commit module to Git after each Pass |
8:38PM |
0 |
[RFC] Formalizing FileCheck Features |
8:29PM |
3 |
[RFC] Formalizing FileCheck Features |
7:23PM |
0 |
RFC: Pass Execution Instrumentation interface |
6:47PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:41PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:29PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:26PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:23PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:18PM |
2 |
RFC: Pass Execution Instrumentation interface |
5:49PM |
3 |
Commit module to Git after each Pass |
4:58PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
4:36PM |
3 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
2:01PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
12:44PM |
0 |
RFC: Atomic LL/SC loops in LLVM revisited |
11:32AM |
2 |
RFC: Atomic LL/SC loops in LLVM revisited |
10:44AM |
3 |
runStaticConstructorsDestructors() causes crash on exit |
9:28AM |
0 |
RFC: Atomic LL/SC loops in LLVM revisited |
7:41AM |
0 |
[sanitizer] When do we expect PIC macro to be defined? |
1:36AM |
1 |
pseudo Instruction usage |
|
Wednesday June 13 2018 |
Time | Replies | Subject |
11:17PM |
0 |
Question about a May-alias case |
10:50PM |
2 |
Question about a May-alias case |
10:37PM |
0 |
RFC: Atomic LL/SC loops in LLVM revisited |
9:19PM |
1 |
RFC: cleanup in Transforms/Utils |
9:09PM |
0 |
RFC: cleanup in Transforms/Utils |
9:04PM |
2 |
RFC: cleanup in Transforms/Utils |
9:01PM |
0 |
DWARF v5 - compiler work update |
8:43PM |
0 |
RFC: Pass Execution Instrumentation interface |
7:48PM |
2 |
RFC: Pass Execution Instrumentation interface |
6:59PM |
0 |
Question about a May-alias case |
6:52PM |
0 |
RFC: Bug-closing protocol |
6:26PM |
2 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:18PM |
0 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
6:13PM |
0 |
RFC: Pass Execution Instrumentation interface |
6:03PM |
4 |
RFC: Pass Execution Instrumentation interface |
5:15PM |
0 |
RFC: Pass Execution Instrumentation interface |
5:03PM |
0 |
RFC: Pass Execution Instrumentation interface |
4:58PM |
0 |
RFC: Bug-closing protocol |
4:46PM |
4 |
RFC: Pass Execution Instrumentation interface |
3:53PM |
0 |
IR to binary address mapping |
3:42PM |
12 |
RFC: Atomic LL/SC loops in LLVM revisited |
3:11PM |
2 |
IR to binary address mapping |
3:05PM |
0 |
IR to binary address mapping |
2:01PM |
0 |
ModulePass cannot be registered as EarlyAsPossible |
1:56PM |
4 |
[lldb-dev] Adding DWARF5 accelerator table support to llvm |
12:58PM |
2 |
Question about a May-alias case |
12:38PM |
0 |
RFC: Pass Execution Instrumentation interface |
11:41AM |
0 |
ModulePass cannot be registered as EarlyAsPossible |
9:31AM |
1 |
Cloning a function from one module to another module |
7:09AM |
2 |
IR to binary address mapping |
5:11AM |
2 |
RFC: Bug-closing protocol |
12:59AM |
4 |
Success: Bring-up of LLVM/clang-built Linux ARM(32-bit) kernel for Android - Nexus 5 |
12:56AM |
0 |
Success : VirtualBox(clang-built): Ubuntu 17.10 x86_64(clang-built kernel/modules) |
12:49AM |
0 |
RFC: Bug-closing protocol |
12:48AM |
2 |
RFC: Bug-closing protocol |
|
Tuesday June 12 2018 |
Time | Replies | Subject |
9:24PM |
1 |
Strange error after doing transformation on IR level |
8:36PM |
0 |
RFC: Bug-closing protocol |
8:33PM |
0 |
ARM Register Info Bug? |
8:27PM |
0 |
IR to binary address mapping |
8:20PM |
0 |
Hanging sanitizer test linking |
8:07PM |
1 |
RFC: Bug-closing protocol |
6:51PM |
0 |
RFC: Bug-closing protocol |
5:53PM |
0 |
Stack slot LiveIntervals |
5:18PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
3:49PM |
0 |
RFC: Bug-closing protocol |
3:18PM |
0 |
IR to binary address mapping |
2:51PM |
9 |
RFC: Bug-closing protocol |
2:30PM |
4 |
IR to binary address mapping |
2:23PM |
1 |
[RFC] Abstract Parallel IR Optimizations |
1:46PM |
2 |
ModulePass cannot be registered as EarlyAsPossible |
12:47PM |
3 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
12:41PM |
0 |
One more No-alias case on Alias analysis |
11:56AM |
0 |
[RFC] Abstract Parallel IR Optimizations |
10:17AM |
2 |
One more No-alias case on Alias analysis |
9:49AM |
1 |
Question about the status of the IR extensions for OpenMP |
9:17AM |
0 |
Question about the status of the IR extensions for OpenMP |
8:05AM |
2 |
LLVM assembly language |
5:04AM |
0 |
Proper method to initialize all LLVM Internal Data Structures? |
4:59AM |
2 |
Proper method to initialize all LLVM Internal Data Structures? |
12:31AM |
0 |
XRay feature – pid reporting |
12:27AM |
0 |
XRay feature – fdr log flushing |
12:22AM |
0 |
XRay FDR mode doesn’t log main thread calls |
|
Monday June 11 2018 |
Time | Replies | Subject |
9:50PM |
2 |
XRay feature – fdr log flushing |
9:49PM |
2 |
XRay feature – pid reporting |
9:49PM |
1 |
XRAY_OPTIONS variable does not enable FDR mode and log flushing |
9:19PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
9:04PM |
2 |
RFC: Pass Execution Instrumentation interface |
8:51PM |
0 |
LLVM Weekly - #232, June 11th 2018 |
7:33PM |
0 |
One more No-alias case on Alias analysis |
7:01PM |
1 |
Best practices for using update_*_test_checks.py |
5:06PM |
4 |
One more No-alias case on Alias analysis |
3:59PM |
2 |
Question about the status of the IR extensions for OpenMP |
3:58PM |
1 |
Register Rematerialization |
3:47PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
1:05PM |
0 |
TableGen: more powerful generic tables as successor of SearchableTable |
9:53AM |
0 |
LoopVectorize fails to vectorize code with condition on reduction |
9:42AM |
0 |
[RFC] Porting MachinePipeliner to AArch64+SVE |
9:40AM |
2 |
LoopVectorize fails to vectorize code with condition on reduction |
|
Sunday June 10 2018 |
Time | Replies | Subject |
1:34PM |
3 |
Proposed patches for Android Build errors |
7:01AM |
1 |
Kaleidoscope Tutorial Chapter #4: externs crash REPL |
|
Saturday June 9 2018 |
Time | Replies | Subject |
11:55PM |
0 |
Error llvm interpreter for posix_memalign |
2:50PM |
1 |
[RFC] Porting MachinePipeliner to AArch64+SVE |
9:22AM |
0 |
llvm interpreter error with polybench |
9:06AM |
0 |
Problems compiling clang with clang++ |
6:37AM |
0 |
Fwd: InstrEmitter::CreateVirtualRegisters handling of CopyToReg |
6:25AM |
0 |
Fail to install llvm/clang on debian |
|
Friday June 8 2018 |
Time | Replies | Subject |
10:02PM |
0 |
Retrieving the name of a indirect virtual method call in LLVM pass |
9:59PM |
1 |
Retrieving the name of a indirect virtual method call in LLVM pass |
8:23PM |
2 |
XRay FDR mode doesn’t log main thread calls |
6:37PM |
0 |
RFC: Pass Execution Instrumentation interface |
6:06PM |
0 |
Retrieving the name of a indirect virtual method call in LLVM pass |
5:36PM |
2 |
RFC: Pass Execution Instrumentation interface |
5:04PM |
0 |
[RFC] Porting MachinePipeliner to AArch64+SVE |
3:24PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
2:57PM |
1 |
C interface with XRay |
2:56PM |
1 |
[GSoC][DebugInfo] SROA debug experience and dexter thoughts |
2:11PM |
4 |
[RFC] Porting MachinePipeliner to AArch64+SVE |
1:12PM |
1 |
[GSoC] [RFC] A new dominator tree updater for LLVM |
12:13PM |
2 |
Fail to install llvm/clang on debian |
7:18AM |
0 |
RFC: Pass Execution Instrumentation interface |
7:10AM |
2 |
RFC: Pass Execution Instrumentation interface |
6:12AM |
0 |
RFC: Pass Execution Instrumentation interface |
4:57AM |
0 |
[RFC] Abstract Parallel IR Optimizations |
3:34AM |
0 |
[7.0.0 Release] Schedule proposal |
12:06AM |
0 |
Sub-optimal register allocation |
|
Thursday June 7 2018 |
Time | Replies | Subject |
10:20PM |
0 |
[lld] ObjFile::createRegular is oblivious of PendingComdat |
9:52PM |
2 |
[lld] ObjFile::createRegular is oblivious of PendingComdat |
9:50PM |
0 |
[lld] ObjFile::createRegular is oblivious of PendingComdat |
9:43PM |
2 |
[lld] ObjFile::createRegular is oblivious of PendingComdat |
8:58PM |
0 |
[GSoC] [RFC] A new dominator tree updater for LLVM |
6:23PM |
1 |
[Release-testers] 6.0.1-rc2 has been tagged |
6:17PM |
0 |
Matching ConstantFPSDNode tablegen |
5:45PM |
2 |
Matching ConstantFPSDNode tablegen |
5:16PM |
0 |
[Release-testers] 6.0.1-rc2 has been tagged |
4:56PM |
0 |
[cfe-dev] [7.0.0 Release] Schedule proposal |
4:14PM |
0 |
RFC: Pass Execution Instrumentation interface |
4:10PM |
3 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
4:10PM |
0 |
Fwd: job opportunities for R&D on Clang/LLVM to support new heterogeneous/parallel/soc architectures | 6-Jun-2018 |
3:48PM |
2 |
RFC: Pass Execution Instrumentation interface |
3:12PM |
2 |
[Release-testers] 6.0.1-rc2 has been tagged |
3:11PM |
0 |
RFC: Pass Execution Instrumentation interface |
1:51PM |
2 |
XRay TID mismatch when forking |
1:36PM |
4 |
[7.0.0 Release] Schedule proposal |
10:25AM |
2 |
[RFC] Abstract Parallel IR Optimizations |
5:52AM |
1 |
FW: [RFC] Abstract Parallel IR Optimizations |
5:43AM |
1 |
How to get optimization remarks while testing with lnt in llvm |
12:36AM |
0 |
Porting OptBisect to New Pass Manager |
12:00AM |
5 |
RFC: Pass Execution Instrumentation interface |
|
Wednesday June 6 2018 |
Time | Replies | Subject |
9:52PM |
0 |
LLVM buildmaster will be restarted tonight |
9:26PM |
2 |
Porting OptBisect to New Pass Manager |
9:07PM |
1 |
Mach-O support in lld: what are the known issues? |
8:37PM |
0 |
Mach-O support in lld: what are the known issues? |
7:55PM |
0 |
[Release-testers] 6.0.1-rc2 has been tagged |
6:40PM |
2 |
Mach-O support in lld: what are the known issues? |
6:10PM |
0 |
Mach-O support in lld: what are the known issues? |
4:36PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
4:21PM |
0 |
[RFC] Abstract Parallel IR Optimizations |
3:33PM |
0 |
How to make the induction variable local when extracting a loop into a function ? |
1:10PM |
0 |
job opportunities for R&D on Clang/LLVM to support new heterogeneous/parallel/soc architectures | 6-Jun-2018 |
12:50PM |
0 |
LLVM IR question |
9:20AM |
2 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
|
Tuesday June 5 2018 |
Time | Replies | Subject |
11:40PM |
2 |
LLVM IR question |
10:17PM |
0 |
[SROA][DebugInfo][GSoC] Testing SROA on amalgamated sqlite source |
9:44PM |
2 |
Mach-O support in lld: what are the known issues? |
9:41PM |
0 |
How to get optimization remarks while testing with lnt in llvm |
9:40PM |
0 |
[RFC] Removing lld-link -msvclto option |
8:50PM |
1 |
lld mishandling R_X86_64_PC32 relocations |
7:34PM |
0 |
lld mishandling R_X86_64_PC32 relocations |
7:25PM |
0 |
Unit Tests CMake configuration |
7:08PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
6:30PM |
1 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
6:25PM |
3 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
6:05PM |
1 |
llvm-dev not idenitifying me? |
5:47PM |
0 |
llvm-dev not idenitifying me? |
5:47PM |
0 |
[Release-testers] 6.0.1-rc2 has been tagged |
5:38PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
5:33PM |
2 |
lld mishandling R_X86_64_PC32 relocations |
5:02PM |
2 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
4:45PM |
0 |
[VPlan] about vectorization factor selection |
4:24PM |
0 |
llvm-dev not idenitifying me? |
3:52PM |
0 |
[LLD] Lack of REQUIRES causing test failures when not building with x86 support |
3:47PM |
2 |
[LLD] Lack of REQUIRES causing test failures when not building with x86 support |
3:29PM |
0 |
Booth volunteers needed for Grace Hopper Conference |
3:27PM |
5 |
llvm-dev not idenitifying me? |
3:26PM |
0 |
Mach-O support in lld: what are the known issues? |
3:23PM |
0 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
3:18PM |
0 |
Mach-O support in lld: what are the known issues? |
2:05PM |
2 |
Booth volunteers needed for Grace Hopper Conference |
1:15PM |
14 |
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths |
9:37AM |
1 |
[regalloc] How to access the Virtual Registers Map? |
9:13AM |
1 |
[lldb-dev] LLVM-C |
8:02AM |
3 |
Unit Tests CMake configuration |
6:47AM |
0 |
LLVM Social - Shanghai: July 1st, 2018 |
4:49AM |
2 |
How to get optimization remarks while testing with lnt in llvm |
4:33AM |
1 |
DiagnosticInfo and SCEV |
3:52AM |
0 |
DiagnosticInfo and SCEV |
1:14AM |
2 |
DiagnosticInfo and SCEV |
|
Monday June 4 2018 |
Time | Replies | Subject |
11:37PM |
0 |
June LLVM bay-area social is this Thursday! |
11:06PM |
4 |
Mach-O support in lld: what are the known issues? |
9:18PM |
2 |
[SROA][DebugInfo][GSoC] Testing SROA on amalgamated sqlite source |
7:29PM |
0 |
LLVM Weekly - #231, June 4th 2018 |
4:12PM |
0 |
AnalysisGroup Pass Help |
4:01PM |
5 |
6.0.1-rc2 has been tagged |
3:53PM |
0 |
[LLD] Lack of REQUIRES causing test failures when not building with x86 support |
3:05PM |
0 |
Deprecating ADDC/ADDE/SUBC/SUBE |
3:01PM |
0 |
Deprecating ADDC/ADDE/SUBC/SUBE |
2:49PM |
3 |
[LLD] Lack of REQUIRES causing test failures when not building with x86 support |
12:51PM |
1 |
reusing an ExecutionEngine instance |
9:53AM |
0 |
How to get optimization remarks while testing with lnt in llvm |
9:42AM |
0 |
Miscompilation while switching from clang-4 to clang-5 |
8:00AM |
0 |
Loop pass manager question (Legacy) |
5:18AM |
1 |
Function start address |
5:14AM |
0 |
Function start address |
|
Sunday June 3 2018 |
Time | Replies | Subject |
9:45PM |
0 |
[WebAssembly] lld dynamic loader |
8:35PM |
2 |
Retrieving the name of a indirect virtual method call in LLVM pass |
7:08PM |
2 |
Function start address |
6:54AM |
0 |
Function start address |
|
Saturday June 2 2018 |
Time | Replies | Subject |
4:04PM |
0 |
LoopIdiomRecognize is not recognizing the ctpop idiom |
11:24AM |
2 |
LoopIdiomRecognize is not recognizing the ctpop idiom |
10:59AM |
0 |
A BNF grammar for LLVM IR assembly |
8:32AM |
1 |
Why doesn't tail recursion elimination work? |
5:34AM |
2 |
Function start address |
5:30AM |
1 |
Function start address |
|
Friday June 1 2018 |
Time | Replies | Subject |
9:14PM |
2 |
[VPlan] about vectorization factor selection |
5:32PM |
2 |
Miscompilation while switching from clang-4 to clang-5 |
5:16PM |
0 |
Programmatically Toggle Specific LLVM Optimizations |
3:46PM |
1 |
Update thin-lto cache file atimes when on windows |
3:02PM |
2 |
Programmatically Toggle Specific LLVM Optimizations |
3:00PM |
0 |
Function start address |
1:47PM |
0 |
[Kaleidoscope] symbol(s) not found during compiling |
1:31PM |
3 |
[Kaleidoscope] symbol(s) not found during compiling |
1:00PM |
2 |
[WebAssembly] lld dynamic loader |
11:09AM |
1 |
[VPlan] Dead instructions are invariant to VFs when build vplan |
10:36AM |
3 |
Function start address |
10:21AM |
0 |
[VPlan] Dead instructions are invariant to VFs when build vplan |
9:56AM |
2 |
[VPlan] Dead instructions are invariant to VFs when build vplan |
7:06AM |
0 |
Miscompilation while switching from clang-4 to clang-5 |
7:01AM |
1 |
endianness and bit fields in struct{} |
12:29AM |
1 |
Proposal for address-significance tables for --icf=safe |
12:13AM |
0 |
Proposal for address-significance tables for --icf=safe |
12:06AM |
2 |
Proposal for address-significance tables for --icf=safe |