llvm dev - Jun 2018 - Target hardware loop instruction via intrinsics

Hi,

Hexagon has a MIR pass for detecting loops that map onto hardware support.
I think a similar approach would be viable for my target but am put off by
the complexity of determining whether a given loop is legal to transform.

Instead, I would like to pass the responsibility for determining legality
onto the C programmer who is assumed sufficiently familiar with the
architecture.

I think this would require a pair of intrinsics to denote the start and end
of the loop. Is there a reasonable way to model this in llvm?

If not, would anyone suggest a compiler programmer friendly, even if
application programmer hostile, way to target a loop instruction with many
constraints on validity.

Thanks!

Jon
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On 06/21/2018 01:07 PM, Jon Chesterfield via llvm-dev
wrote:
> Hi,
>
> Hexagon has a MIR pass for detecting loops that map onto hardware
> support. I think a similar approach would be viable for my target but
> am put off by the complexity of determining whether a given loop is
> legal to transform.
I think that it is easier to do this legality checking at the IR level
(where we can take advantage of the ScalarEvolution analysis). This is
what PowerPC does (see lib/Target/PowerPC/PPCCTRLoops.cpp). I recommend
that you take this approach if possible.

 -Hal
>
> Instead, I would like to pass the responsibility for determining
> legality onto the C programmer who is assumed sufficiently familiar
> with the architecture.
>
> I think this would require a pair of intrinsics to denote the start
> and end of the loop. Is there a reasonable way to model this in llvm?
>
> If not, would anyone suggest a compiler programmer friendly, even if
> application programmer hostile, way to target a loop instruction with
> many constraints on validity.
>
> Thanks!
>
> Jon
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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That's a good idea, thanks!

On Thu, Jun 21, 2018 at 7:25 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 06/21/2018 01:07 PM, Jon Chesterfield via llvm-dev wrote:
>
> Hi,
>
> Hexagon has a MIR pass for detecting loops that map onto hardware support.
> I think a similar approach would be viable for my target but am put off by
> the complexity of determining whether a given loop is legal to transform.
>
>
> I think that it is easier to do this legality checking at the IR level
> (where we can take advantage of the ScalarEvolution analysis). This is what
> PowerPC does (see lib/Target/PowerPC/PPCCTRLoops.cpp). I recommend that
> you take this approach if possible.
>
>  -Hal
>
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Hi Jon,

On Thu, 21 Jun 2018 at 19:08, Jon Chesterfield via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> I think this would require a pair of intrinsics to denote the start and end
of the loop. Is there a reasonable way to model this in llvm?
Have you looked into how OpenMP vectorization pragmas are handled yet?
I only glanced at it out of curiosity the other week but it looks like
they attach some "!loop" metadata to the back-edge branch of the loop
involved. It looks string-based and so reasonably extensible, and
legality is already one of the bits of information encoded.

What I don't know is whether that's available to MIR if you end up
doing your work there. The main vectorizers act on IR.

Cheers.

Tim.