search for: arminstrthumb

...ildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1).add(predOps(ARMCC::AL); But how do I know how many and which condition codes each instruction needs? [MOVi takes 3 operands relating to the condition code (all after the immediate)] There is no info about that in the ARMInstrThumb.td file. -Julius On 03/23/2018 12:18 AM, Tom Stellard wrote: > On 03/22/2018 09:29 AM, Julius Hiller via llvm-dev wrote: >> Hello everyone, >> >> I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. >...

...BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); > > I get the following error: > > .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. > According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm and there is no explicit destination register, so what you want is: BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1); -Tom > Which even after hours I can't make sense why the operand kind is wrong. > > Ano...

Hello everyone, I'm working on a MachineFunctionPass that inserts a list of instructions into an Module so a later Pass can work on them. To do so I load a dummy .ll file created from a main stub, create the needed function stubs (ModulePass), insert Blocks and create instructions using BuildMI. I started with branch instructions:     const TargetMachine &TM = MF.getTarget();

The tBLXr description in ARMInstrThumb.td is not complete. It doesn't set the register operand. -- // koan-sin tan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110429/5f375f23/attachment.html> -------------- next part -------------- A...

...ldr r6, #380, However the value for ldr is "an 8-bit value that is multiplied by 4 and added to the value of the PC to form the memory address" (via ARMARM), so that the correct mnemonics is: ldr r6, [pc, #380] (provided by Apple's otool). I've traced the issue down to ARMInstrThumb.td: // A8.6.57 & A8.6.60 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, t_addrmode_is4, AddrModeT1_4, IIC_iLoad_r, IIC_iLoad_i, "ldr", UnOpFrag<(load node:$Src)>&...

Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2 instead of t. The definition of tA...

...is not of type Slot_EarlyClobber since the MI being replaced is a COPY with no EC ops. I've also found a way for you to reproduce this error in a simple way with the ARM backend with -march=thumb: Just add "Constraints = "@earlyclobber $Rt" in" to the tLDRspi instruction in ARMInstrThumb.td (around line 620) and compile the following code with llc at -O3: target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "armv4t-generic-generic" define float @f3(float %days) n...

On Jul 15, 2012, at 9:20 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Jakob, one more hint, I've placed some asserts around the code you added and noticed that the InlineSpiller::insertReload() function is not being called. > > 2012/7/14 Borja Ferrer <borja.ferav at gmail.com> > Hello Jakob, > > I'm still getting the error, I can give you any other

Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot use them