llvm dev - Dec 2016 - Assign different RegClasses to a virtual register based on 'uniform' attribute?

Hi,

I am working on a new LLVM target for Intel GPU, which also has same kind
of scalar/vector register classes used in AMDGPU target. Like for a i32
virtual register, it will be held in scalar register if its value is
uniform across a wavefront/warp, otherwise it will be in a vector register.
Does AMDGPU already done this? I read the code, but I didn't figure out how
to do this. Anybody has idea on this?

- Ruiling
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20161220/ae611074/attachment.html>

On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song
wrote:
> Hi,
> 
> I am working on a new LLVM target for Intel GPU, which also has same kind
> of scalar/vector register classes used in AMDGPU target. Like for a i32
> virtual register, it will be held in scalar register if its value is
> uniform across a wavefront/warp, otherwise it will be in a vector register.
> Does AMDGPU already done this? I read the code, but I didn't figure out
how
> to do this. Anybody has idea on this?
> 
In the AMDGPU backend we select everything we can to scalar
instructions, and then after instruction selection, we move
non-uniform values to the vector ALU.  This is done by
the SIFixSGPRCopiesPass, which relies heavily on
SIInstrInfo::moveToVALU().

-Tom
> - Ruiling

2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at
stellard.net>:
>
> On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote:
> > Hi,
> >
> > I am working on a new LLVM target for Intel GPU, which also has same
kind
> > of scalar/vector register classes used in AMDGPU target. Like for a
i32
> > virtual register, it will be held in scalar register if its value is
> > uniform across a wavefront/warp, otherwise it will be in a vector
register.
> > Does AMDGPU already done this? I read the code, but I didn't
figure out
how
> > to do this. Anybody has idea on this?
> >
>
> In the AMDGPU backend we select everything we can to scalar
> instructions, and then after instruction selection, we move
> non-uniform values to the vector ALU.  This is done by
> the SIFixSGPRCopiesPass, which relies heavily on
> SIInstrInfo::moveToVALU().
Hi Tom,

I take a look at the code, it looks like a good idea. It really helps me a
lot. Thanks Tom! I have a question for the code, why it only pass copy-like
instructions as TopInst to moveToALU()? Is there any special reason to do
like this? I thought that iterating through all the MIs and fix regClass if
needed would be ok. Am I thinking it too simple?

- Ruiling
>
> -Tom
>
> > - Ruiling



-- 
- Ruiling
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20161221/62bf3cc9/attachment.html>