search for: movetovalu

Displaying 6 results from an estimated 6 matches for "movetovalu".

2016 Dec 20
0
Assign different RegClasses to a virtual register based on 'uniform' attribute?
...gure out how > to do this. Anybody has idea on this? > In the AMDGPU backend we select everything we can to scalar instructions, and then after instruction selection, we move non-uniform values to the vector ALU. This is done by the SIFixSGPRCopiesPass, which relies heavily on SIInstrInfo::moveToVALU(). -Tom > - Ruiling
2016 Dec 21
0
Assign different RegClasses to a virtual register based on 'uniform' attribute?
...t; > > > > In the AMDGPU backend we select everything we can to scalar > > instructions, and then after instruction selection, we move > > non-uniform values to the vector ALU. This is done by > > the SIFixSGPRCopiesPass, which relies heavily on > > SIInstrInfo::moveToVALU(). > > Hi Tom, > > I take a look at the code, it looks like a good idea. It really helps me a lot. Thanks Tom! I have a question for the code, why it only pass copy-like instructions as TopInst to moveToALU()? Is there any special reason to do like this? I thought that iterating throu...
2016 Dec 21
3
Assign different RegClasses to a virtual register based on 'uniform' attribute?
...body has idea on this? > > > > In the AMDGPU backend we select everything we can to scalar > instructions, and then after instruction selection, we move > non-uniform values to the vector ALU. This is done by > the SIFixSGPRCopiesPass, which relies heavily on > SIInstrInfo::moveToVALU(). Hi Tom, I take a look at the code, it looks like a good idea. It really helps me a lot. Thanks Tom! I have a question for the code, why it only pass copy-like instructions as TopInst to moveToALU()? Is there any special reason to do like this? I thought that iterating through all the MIs and f...
2016 Dec 21
1
Assign different RegClasses to a virtual register based on 'uniform' attribute?
...t; In the AMDGPU backend we select everything we can to scalar > > > instructions, and then after instruction selection, we move > > > non-uniform values to the vector ALU. This is done by > > > the SIFixSGPRCopiesPass, which relies heavily on > > > SIInstrInfo::moveToVALU(). > > > > Hi Tom, > > > > I take a look at the code, it looks like a good idea. It really helps me a lot. Thanks Tom! I have a question for the code, why it only pass copy-like instructions as TopInst to moveToALU()? Is there any special reason to do like this? I thought...
2016 Dec 20
2
Assign different RegClasses to a virtual register based on 'uniform' attribute?
Hi, I am working on a new LLVM target for Intel GPU, which also has same kind of scalar/vector register classes used in AMDGPU target. Like for a i32 virtual register, it will be held in scalar register if its value is uniform across a wavefront/warp, otherwise it will be in a vector register. Does AMDGPU already done this? I read the code, but I didn't figure out how to do this. Anybody has
2016 Dec 23
0
Assign different RegClasses to a virtual, register based on 'uniform' attribute?
...t;>> In the AMDGPU backend we select everything we can to scalar >>> instructions, and then after instruction selection, we move >>> non-uniform values to the vector ALU. This is done by >>> the SIFixSGPRCopiesPass, which relies heavily on >>> SIInstrInfo::moveToVALU(). >> Hi Tom, >> >> I take a look at the code, it looks like a good idea. It really helps me > a lot. Thanks Tom! I have a question for the code, why it only pass > copy-like instructions as TopInst to moveToALU()? Is there any special > reason to do like this? I thought...