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> -----Original Message----- > From: meinersbur at googlemail.com [mailto:meinersbur at googlemail.com] On > Behalf Of Michael Kruse > Sent: Wednesday, October 18, 2017 1:18 PM > To: Song, Ruiling <ruiling.song at intel.com> > Cc: Michael Kruse <llvm at meinersbur.de>; llvm-dev at lists.llvm.org > Subject: Re: Possible bug of Alias Analysis? > > 2017-10-18 4:48 GMT+02:00 Song, Ruiling <ruiling.song at intel.com>: > >> -----Original Message----- > &g...

> On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > > > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>: > > > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > > Hi, > > > > &gt...

> -----Original Message----- > From: meinersbur at googlemail.com [mailto:meinersbur at googlemail.com] On > Behalf Of Michael Kruse > Sent: Tuesday, October 17, 2017 3:26 PM > To: Song, Ruiling <ruiling.song at intel.com> > Cc: llvm at meinersbur.de; llvm-dev at lists.llvm.org > Subject: Re: Possible bug of Alias Analysis? > > 2017-10-17 8:45 GMT+02:00 Song, Ruiling <ruiling.song at intel.com>: > > Hi, > > > > I am an out-of-tree user of llvm. I...

On Wed, Dec 21, 2016 at 10:31:57AM -0500, Matt Arsenault wrote: > > > On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > > > > > > > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>: > > > > > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > &g...

2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net>: > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > Hi, > > > > I am working on a new LLVM target for Intel GPU, which also has same kind > > of scalar/vector register classes used in AMDGPU target. Like for a i32 > > virtual register, it will be held in scalar register if its value is > > uniform...

...32 %3, i32* %4, align 4, !tbaa !3 but in fact, they should be aliased as they are writing to/reading from the same buffer. you can run 'opt -S -aa -basicaa -tbaa -gvn aa-bug.ll -o -' to see what happens. I am not sure if we use llvm wrong or is it a bug that we should fix in llvm? Thanks! Ruiling -------------- next part -------------- A non-text attachment was scrubbed... Name: aa-bug.ll Type: application/octet-stream Size: 4090 bytes Desc: aa-bug.ll URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20171017/cc4524a1/attachment.obj>

...e llvm passes like GVN SROA will generate some IR operating on wide integer types like i128 or i512. But the device does not support such kind of data type. Is there any idea on how to lower this kind of IR to only operate on i32 or vector of i32? Or is there any existing code handle this? Thanks! Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140904/7601277d/attachment.html>

Hi, The gpu target I am working on requires the 'value' and 'address' operands of memory store instruction in consecutive register. Anybody has suggestion? - Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160909/e9d330bc/attachment.html>

On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > Hi, > > I am working on a new LLVM target for Intel GPU, which also has same kind > of scalar/vector register classes used in AMDGPU target. Like for a i32 > virtual register, it will be held in scalar register if its value is > uniform across a wavefront/warp, othe...

...%153 = load <2 x i16> addrspace(1)* %152, align 2 going through the use-def chain seems not easy, because the 'add' operation contains two operands, one come from a pointer, the other is an integer offset. I could not know which is at operand 0 and which is at operand 1. Thanks! Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20141119/419f63df/attachment.html>

...from the LLVM IR. This eliminates too-wide integer types by decomposing the > operations. > > However, SROA never produces an integer wider than what was used in the > input IR that I know of... I would be surprised if GVN did this either. > > > On Wed, Sep 3, 2014 at 10:53 PM, Ruiling Song <ruiling.song83 at gmail.com> > wrote: > >> Hi, >> >> I am currently working on an opencl project based on LLVM, the target >> device is 32bit. >> I met a problem that some llvm passes like GVN SROA will generate some IR >> operating >> on...

...el functions and optimizations > (Jingyue Wu via llvm-dev) > 2. Re: llvm/cuda: Indentify kernel functions and optimizations > (Gurunath Kadam via llvm-dev) > 3. Re: Assign different RegClasses to a virtual register based > on 'uniform' attribute? (Ruiling Song via llvm-dev) > 4. Re: Assign different RegClasses to a virtual register based > on 'uniform' attribute? (Ruiling Song via llvm-dev) > 5. Postdoc Positions - LLVM for High-Performance Computing > (Hal Finkel via llvm-dev) > 6. struct bitfield re...

...aybe I can cancel it somehow with a flag or by doing some code editing? Can you point me to which passes may do that? I'm working on editing a backend that can't work with anything larger than 32 bits. Does the legalize stage work on IR code? Maybe i can use that? On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote: LLVM contains some optimization pass that will generate instructions operate on i64 or even i128 and more. The upstream backend utilize the legalize stage that can break it into instructions with smaller integer types if the target machine does not su...

...to allocate the sub-registers, just operate them as a whole. right? Yes, it looks really easy for divergent registers. But I think then I would lose the ability to allocate uniform register. Am I right? Is there any way to allocate uniform register as well as allocate divergent register? Thanks! Ruiling 2016-08-23 0:32 GMT+08:00 <escha at apple.com>: > > On Aug 22, 2016, at 6:46 AM, Ruiling Song via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hello Everyone, > > I am trying to make a new LLVM backend target for Intel GPU. > I would start from targeting...

...with a > flag or by doing some code editing? Can you point me to which passes may do > that? > > I'm working on editing a backend that can't work with anything larger than > 32 bits. Does the legalize stage work on IR code? Maybe i can use that? > On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > LLVM contains some optimization pass that will generate instructions > operate on i64 or even i128 and more. The upstream backend utilize the > legalize stage that can break it into instructions with smaller integer > types if the...

...e books to study about compiler techniques? > If you guys find troubled to answer my questions, can you guys at least recommend me some sources or documentations so that i can look into myself? > > Thanks in advance. > Chuan > > > > > > From: Song, Ruiling <ruiling.song at intel.com> > Sent: Tuesday, September 12, 2017 9:17 AM > To: jin chuan see; Matthias Braun > Cc: llvm-dev at lists.llvm.org > Subject: RE: [llvm-dev] Live Register Spilling > > Running llc with ‘-verify-machineinstrs’ may tell you which instruction break t...

...in AMDGPU target. Like for a i32 virtual register, it will be held in scalar register if its value is uniform across a wavefront/warp, otherwise it will be in a vector register. Does AMDGPU already done this? I read the code, but I didn't figure out how to do this. Anybody has idea on this? - Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161220/ae611074/attachment.html>

...t;IntelGPU", [i32, f32], 32, (add gpr_d_simd8)> { } This is easy for me to define the register alias information. But it won't works! the tablegen exit and tells me: "error:Ran out of lanemask bits to represent subregister sub1_then_sub1" Anybody know what's wrong here? - Ruiling 2016-08-23 11:45 GMT+08:00 <escha at apple.com>: > If I understand right, on this arch, ‘uniform’ refers to values that only > take one lane of register file instead of SIMD-width lanes, and they > *share* the same region of the register file as non-uniform values. This is > in...

...subd#Index :SubRegIndex<32, !shl(Index, 5)>; //used as SubRegIndex when declaring gpr_d_simd8 def subw#Index: SubRegIndex<16, !shl(Index, 4)>; //used as SubRegIndex when declaring gpr_w_simd8 ... } If anything I am not saying clear, just reply the mail. Thanks for any help! Thanks! Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160822/7e9761ee/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: IntelGPURegisterInfo.td Type: applicatio...

Running llc with '-verify-machineinstrs' may tell you which instruction break the SSA form. Ruiling From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of jin chuan see via llvm-dev Sent: Monday, September 11, 2017 10:02 AM To: Matthias Braun <mbraun at apple.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Live Register Spilling Sorry about the previous messag...