mats petersson via llvm-dev
2016-May-24 17:03 UTC
[llvm-dev] Liveness of AL, AH and AX in x86 backend
On several variants of x86 processors, mixing `ah`, `al` and `ax` as source/destination in the same dependency chain will have some penalties, so for THOSE processors, there is a benefit to NOT use `al` and `ah` to reflect parts of `ax` - I believe this is caused by the fact that the processor doesn't ACTUALLY see these as parts of a bigger register internally, and will execute two independent dependency chains, UNTIL you start using `ax` as one register. At this point, the processor has to make sure both of dependency chains for `al` and `ah` have been complete, and that the merged value is available in `ax`. If the processor uses `cl` and `al`, this sort of problem is avoided. <<Quote from Intel Optimisation guide, page 3-44 http://www.intel.co.uk/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf A partial register stall happens when an instruction refers to a register, portions of which were previously modified by other instructions. For example, partial register stalls occurs with a read to AX while previous instructions stored AL and AH, or a read to EAX while previous in struction modified AX. The delay of a partial register stall is small in processors based on Intel Core and NetBurst microarchitectures, and in Pentium M processor (with CPUID signature family 6, model 13), Intel Core Solo, and Intel Core Duo processors. Pentium M processors (CPUID signature with family 6, model 9) and the P6 family incur a large penalty. <<Enq quote>> So for compact code, yes, it's probably an advantage. For SOME processors in the x86 range, not so good for performance. Whether LLVM has the information as to WHICH processor models have such penalties (or better yet, can determine the amount of time lost for this sort of operation), I'm not sure. It's obviously something that CAN be programmed into a compiler, it's just a matter of understanding the effort vs. reward factor for this particular type of optimisation, compared to other things that could be done to improve the quality of the code generated. -- Mats On 24 May 2016 at 17:09, Smith, Kevin B via llvm-dev < llvm-dev at lists.llvm.org> wrote:> Try using x86 mode rather than Intel64 mode. I have definitely gotten it > to use both ah and al in 32 bit x86 code generation. > In particular, I have seen that in loops for both the spec2000 and > spec2006 versions of bzip. It can happen, but it does only rarely. > > Kevin Smith > > >-----Original Message----- > >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of > >Krzysztof Parzyszek via llvm-dev > >Sent: Tuesday, May 24, 2016 8:04 AM > >To: LLVM Dev <llvm-dev at lists.llvm.org> > >Subject: [llvm-dev] Liveness of AL, AH and AX in x86 backend > > > >I'm trying to see how the x86 backend deals with the relationship > >between AL, AH and AX, but I can't get it to generate any code that > >would expose an interesting scenario. > > > >For example, I wrote this piece: > > > >typedef struct { > > char x, y; > >} struct_t; > > > >struct_t z; > > > >struct_t foo(char *p) { > > struct_t s; > > s.x = *p++; > > s.y = *p; > > z = s; > > s.x++; > > return s; > >} > > > >But the output at -O2 is > > > >foo: # @foo > > .cfi_startproc > ># BB#0: # %entry > > movb (%rdi), %al > > movzbl 1(%rdi), %ecx > > movb %al, z(%rip) > > movb %cl, z+1(%rip) > > incb %al > > shll $8, %ecx > > movzbl %al, %eax > > orl %ecx, %eax > > retq > > > > > >I was hoping it would do something along the lines of > > > > movb (%rdi), %al > > movb 1(%rdi), %ah > > movh %ax, z(%rip) > > incb %al > > retq > > > > > >Why is the x86 backend not getting this code? Does it know that AH:AL > >AX? > > > >-Krzysztof > > > > > > > >-- > >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > >hosted by The Linux Foundation > >_______________________________________________ > >LLVM Developers mailing list > >llvm-dev at lists.llvm.org > >http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160524/4c39a269/attachment.html>
Krzysztof Parzyszek via llvm-dev
2016-May-24 17:10 UTC
[llvm-dev] Liveness of AL, AH and AX in x86 backend
Then let me shift focus from performance to size. With either optsize or minsize, the output is still the same. As per the subject, I'm not really interested in the quality of the final code, but in the way that the x86 target deals with the structural relationship between these registers. Specifically, I'd like to see if it would generate implicit defs/uses for AX on defs/uses of AH/AL. I looked in the X86 sources and I didn't find code that would make me certain, but I'm not too familiar with that backend. Having a testcase to work with would make it a lot easier for me. -Krzysztof On 5/24/2016 12:03 PM, mats petersson wrote:> On several variants of x86 processors, mixing `ah`, `al` and `ax` as > source/destination in the same dependency chain will have some > penalties, so for THOSE processors, there is a benefit to NOT use `al` > and `ah` to reflect parts of `ax` - I believe this is caused by the fact > that the processor doesn't ACTUALLY see these as parts of a bigger > register internally, and will execute two independent dependency chains, > UNTIL you start using `ax` as one register. At this point, the processor > has to make sure both of dependency chains for `al` and `ah` have been > complete, and that the merged value is available in `ax`. If the > processor uses `cl` and `al`, this sort of problem is avoided. > > <<Quote from Intel Optimisation guide, page 3-44 > http://www.intel.co.uk/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf > > A partial register stall happens when an instruction refers to a > register, portions of > which were previously modified by other instructions. For example, > partial register > stalls occurs with a read to AX while previous instructions stored AL > and AH, or a read > to EAX while previous in > struction modified AX. > The delay of a partial register stall is small in processors based on > Intel Core and > NetBurst microarchitectures, and in Pentium M processor (with CPUID > signature > family 6, model 13), Intel Core Solo, > and Intel Core Duo processors. Pentium M > processors (CPUID signature with family 6, > model 9) and the P6 family incur a large > penalty. > <<Enq quote>> > > So for compact code, yes, it's probably an advantage. For SOME > processors in the x86 range, not so good for performance. > > Whether LLVM has the information as to WHICH processor models have such > penalties (or better yet, can determine the amount of time lost for this > sort of operation), I'm not sure. It's obviously something that CAN be > programmed into a compiler, it's just a matter of understanding the > effort vs. reward factor for this particular type of optimisation, > compared to other things that could be done to improve the quality of > the code generated. > > -- > Mats > > On 24 May 2016 at 17:09, Smith, Kevin B via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Try using x86 mode rather than Intel64 mode. I have definitely > gotten it to use both ah and al in 32 bit x86 code generation. > In particular, I have seen that in loops for both the spec2000 and > spec2006 versions of bzip. It can happen, but it does only rarely. > > Kevin Smith > > >-----Original Message----- > >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org > <mailto:llvm-dev-bounces at lists.llvm.org>] On Behalf Of > >Krzysztof Parzyszek via llvm-dev > >Sent: Tuesday, May 24, 2016 8:04 AM > >To: LLVM Dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > >Subject: [llvm-dev] Liveness of AL, AH and AX in x86 backend > > > >I'm trying to see how the x86 backend deals with the relationship > >between AL, AH and AX, but I can't get it to generate any code that > >would expose an interesting scenario. > > > >For example, I wrote this piece: > > > >typedef struct { > > char x, y; > >} struct_t; > > > >struct_t z; > > > >struct_t foo(char *p) { > > struct_t s; > > s.x = *p++; > > s.y = *p; > > z = s; > > s.x++; > > return s; > >} > > > >But the output at -O2 is > > > >foo: # @foo > > .cfi_startproc > ># BB#0: # %entry > > movb (%rdi), %al > > movzbl 1(%rdi), %ecx > > movb %al, z(%rip) > > movb %cl, z+1(%rip) > > incb %al > > shll $8, %ecx > > movzbl %al, %eax > > orl %ecx, %eax > > retq > > > > > >I was hoping it would do something along the lines of > > > > movb (%rdi), %al > > movb 1(%rdi), %ah > > movh %ax, z(%rip) > > incb %al > > retq > > > > > >Why is the x86 backend not getting this code? Does it know that > AH:AL > >AX? > > > >-Krzysztof > > > > > > > >-- > >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > >hosted by The Linux Foundation > >_______________________________________________ > >LLVM Developers mailing list > >llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > >http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > >-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
mats petersson via llvm-dev
2016-May-24 17:37 UTC
[llvm-dev] Liveness of AL, AH and AX in x86 backend
What I was trying to say is that in the past, this sort of construct could be quite significantly worse than the "ideal" code (avoiding such partial register things), and as such I expect some effort has gone into AVOIDING using the `al` and `ah` in ways that lead to `ax` being used as a combination thereof. Whilst it may be detrimental for code-size, it's possible that this is so ingrained in the code that it's hard to avoid it producing code like what you posted. Of course, I'm only speculating, and there may be other answers. I'm NOT a "x86-backend guy" (nor any other kind of backend, for that matter - the little I know about compilers is from working on the frontend). I do however, have a fair understanding both of processor architectures and the optimisation of x86-code in general from having worked within AMD for about 10 years and other places where code-generation and optimisation are important. I'm not so hot on the latest x86 processors, as I've been doing most of my recent work with mobile phone systems (not the x86-based variety). But the "partial register stall" is quite old, so I do remember that. -- Mats On 24 May 2016 at 18:10, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote:> Then let me shift focus from performance to size. With either optsize or > minsize, the output is still the same. > > As per the subject, I'm not really interested in the quality of the final > code, but in the way that the x86 target deals with the structural > relationship between these registers. Specifically, I'd like to see if it > would generate implicit defs/uses for AX on defs/uses of AH/AL. I looked > in the X86 sources and I didn't find code that would make me certain, but > I'm not too familiar with that backend. Having a testcase to work with > would make it a lot easier for me. > > -Krzysztof > > > > On 5/24/2016 12:03 PM, mats petersson wrote: > >> On several variants of x86 processors, mixing `ah`, `al` and `ax` as >> source/destination in the same dependency chain will have some >> penalties, so for THOSE processors, there is a benefit to NOT use `al` >> and `ah` to reflect parts of `ax` - I believe this is caused by the fact >> that the processor doesn't ACTUALLY see these as parts of a bigger >> register internally, and will execute two independent dependency chains, >> UNTIL you start using `ax` as one register. At this point, the processor >> has to make sure both of dependency chains for `al` and `ah` have been >> complete, and that the merged value is available in `ax`. If the >> processor uses `cl` and `al`, this sort of problem is avoided. >> >> <<Quote from Intel Optimisation guide, page 3-44 >> >> http://www.intel.co.uk/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf >> >> A partial register stall happens when an instruction refers to a >> register, portions of >> which were previously modified by other instructions. For example, >> partial register >> stalls occurs with a read to AX while previous instructions stored AL >> and AH, or a read >> to EAX while previous in >> struction modified AX. >> The delay of a partial register stall is small in processors based on >> Intel Core and >> NetBurst microarchitectures, and in Pentium M processor (with CPUID >> signature >> family 6, model 13), Intel Core Solo, >> and Intel Core Duo processors. Pentium M >> processors (CPUID signature with family 6, >> model 9) and the P6 family incur a large >> penalty. >> <<Enq quote>> >> >> So for compact code, yes, it's probably an advantage. For SOME >> processors in the x86 range, not so good for performance. >> >> Whether LLVM has the information as to WHICH processor models have such >> penalties (or better yet, can determine the amount of time lost for this >> sort of operation), I'm not sure. It's obviously something that CAN be >> programmed into a compiler, it's just a matter of understanding the >> effort vs. reward factor for this particular type of optimisation, >> compared to other things that could be done to improve the quality of >> the code generated. >> >> -- >> Mats >> >> On 24 May 2016 at 17:09, Smith, Kevin B via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Try using x86 mode rather than Intel64 mode. I have definitely >> gotten it to use both ah and al in 32 bit x86 code generation. >> In particular, I have seen that in loops for both the spec2000 and >> spec2006 versions of bzip. It can happen, but it does only rarely. >> >> Kevin Smith >> >> >-----Original Message----- >> >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org >> <mailto:llvm-dev-bounces at lists.llvm.org>] On Behalf Of >> >Krzysztof Parzyszek via llvm-dev >> >Sent: Tuesday, May 24, 2016 8:04 AM >> >To: LLVM Dev <llvm-dev at lists.llvm.org <mailto: >> llvm-dev at lists.llvm.org>> >> >Subject: [llvm-dev] Liveness of AL, AH and AX in x86 backend >> > >> >I'm trying to see how the x86 backend deals with the relationship >> >between AL, AH and AX, but I can't get it to generate any code that >> >would expose an interesting scenario. >> > >> >For example, I wrote this piece: >> > >> >typedef struct { >> > char x, y; >> >} struct_t; >> > >> >struct_t z; >> > >> >struct_t foo(char *p) { >> > struct_t s; >> > s.x = *p++; >> > s.y = *p; >> > z = s; >> > s.x++; >> > return s; >> >} >> > >> >But the output at -O2 is >> > >> >foo: # @foo >> > .cfi_startproc >> ># BB#0: # %entry >> > movb (%rdi), %al >> > movzbl 1(%rdi), %ecx >> > movb %al, z(%rip) >> > movb %cl, z+1(%rip) >> > incb %al >> > shll $8, %ecx >> > movzbl %al, %eax >> > orl %ecx, %eax >> > retq >> > >> > >> >I was hoping it would do something along the lines of >> > >> > movb (%rdi), %al >> > movb 1(%rdi), %ah >> > movh %ax, z(%rip) >> > incb %al >> > retq >> > >> > >> >Why is the x86 backend not getting this code? Does it know that >> AH:AL >> >AX? >> > >> >-Krzysztof >> > >> > >> > >> >-- >> >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >> >hosted by The Linux Foundation >> >_______________________________________________ >> >LLVM Developers mailing list >> >llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >> >http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> >> > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160524/6c1dd160/attachment.html>
Mehdi Amini via llvm-dev
2016-May-24 20:02 UTC
[llvm-dev] Liveness of AL, AH and AX in x86 backend
Hi, Could you use "MIR" to forge the example you're looking for? -- Mehdi> On May 24, 2016, at 10:10 AM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Then let me shift focus from performance to size. With either optsize or minsize, the output is still the same. > > As per the subject, I'm not really interested in the quality of the final code, but in the way that the x86 target deals with the structural relationship between these registers. Specifically, I'd like to see if it would generate implicit defs/uses for AX on defs/uses of AH/AL. I looked in the X86 sources and I didn't find code that would make me certain, but I'm not too familiar with that backend. Having a testcase to work with would make it a lot easier for me. > > -Krzysztof > > > On 5/24/2016 12:03 PM, mats petersson wrote: >> On several variants of x86 processors, mixing `ah`, `al` and `ax` as >> source/destination in the same dependency chain will have some >> penalties, so for THOSE processors, there is a benefit to NOT use `al` >> and `ah` to reflect parts of `ax` - I believe this is caused by the fact >> that the processor doesn't ACTUALLY see these as parts of a bigger >> register internally, and will execute two independent dependency chains, >> UNTIL you start using `ax` as one register. At this point, the processor >> has to make sure both of dependency chains for `al` and `ah` have been >> complete, and that the merged value is available in `ax`. If the >> processor uses `cl` and `al`, this sort of problem is avoided. >> >> <<Quote from Intel Optimisation guide, page 3-44 >> http://www.intel.co.uk/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf >> >> A partial register stall happens when an instruction refers to a >> register, portions of >> which were previously modified by other instructions. For example, >> partial register >> stalls occurs with a read to AX while previous instructions stored AL >> and AH, or a read >> to EAX while previous in >> struction modified AX. >> The delay of a partial register stall is small in processors based on >> Intel Core and >> NetBurst microarchitectures, and in Pentium M processor (with CPUID >> signature >> family 6, model 13), Intel Core Solo, >> and Intel Core Duo processors. Pentium M >> processors (CPUID signature with family 6, >> model 9) and the P6 family incur a large >> penalty. >> <<Enq quote>> >> >> So for compact code, yes, it's probably an advantage. For SOME >> processors in the x86 range, not so good for performance. >> >> Whether LLVM has the information as to WHICH processor models have such >> penalties (or better yet, can determine the amount of time lost for this >> sort of operation), I'm not sure. It's obviously something that CAN be >> programmed into a compiler, it's just a matter of understanding the >> effort vs. reward factor for this particular type of optimisation, >> compared to other things that could be done to improve the quality of >> the code generated. >> >> -- >> Mats >> >> On 24 May 2016 at 17:09, Smith, Kevin B via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Try using x86 mode rather than Intel64 mode. I have definitely >> gotten it to use both ah and al in 32 bit x86 code generation. >> In particular, I have seen that in loops for both the spec2000 and >> spec2006 versions of bzip. It can happen, but it does only rarely. >> >> Kevin Smith >> >> >-----Original Message----- >> >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org >> <mailto:llvm-dev-bounces at lists.llvm.org>] On Behalf Of >> >Krzysztof Parzyszek via llvm-dev >> >Sent: Tuesday, May 24, 2016 8:04 AM >> >To: LLVM Dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> >> >Subject: [llvm-dev] Liveness of AL, AH and AX in x86 backend >> > >> >I'm trying to see how the x86 backend deals with the relationship >> >between AL, AH and AX, but I can't get it to generate any code that >> >would expose an interesting scenario. >> > >> >For example, I wrote this piece: >> > >> >typedef struct { >> > char x, y; >> >} struct_t; >> > >> >struct_t z; >> > >> >struct_t foo(char *p) { >> > struct_t s; >> > s.x = *p++; >> > s.y = *p; >> > z = s; >> > s.x++; >> > return s; >> >} >> > >> >But the output at -O2 is >> > >> >foo: # @foo >> > .cfi_startproc >> ># BB#0: # %entry >> > movb (%rdi), %al >> > movzbl 1(%rdi), %ecx >> > movb %al, z(%rip) >> > movb %cl, z+1(%rip) >> > incb %al >> > shll $8, %ecx >> > movzbl %al, %eax >> > orl %ecx, %eax >> > retq >> > >> > >> >I was hoping it would do something along the lines of >> > >> > movb (%rdi), %al >> > movb 1(%rdi), %ah >> > movh %ax, z(%rip) >> > incb %al >> > retq >> > >> > >> >Why is the x86 backend not getting this code? Does it know that >> AH:AL >> >AX? >> > >> >-Krzysztof >> > >> > >> > >> >-- >> >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >> >hosted by The Linux Foundation >> >_______________________________________________ >> >LLVM Developers mailing list >> >llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >> >http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >> > > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev