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...ses in locore.s with the definition of the constants $PAGE_SHIFT and $PTESHIFT used in `shr' and `shl' instructions within the macros `fillkpt' and `fillkptphys'. i've tried to cvsup(1) RELENG_4 and RELENG_4_8 every day for over a week now, but kernel builds (as part of a buildworld) don't work anymore. i have set up an area different from the usual /usr/obj/, so i can experiment. if somebody has tips for me, i could do a lot without destroying what's left of my last clean install. locore.s depends on a number of files, one of which is assym.s. assym.s should &quot...

...s at both ends. I have tried very hard to change the type of ends by using 'lend' arguments, but cannot make it. I even tried 'arrows()', but still failed. Following is the code I use: ==================================================== drug.or <- c(1.017,1.437,1.427,2.211) drug.orl <- c(0.715,1.075,1.103,1.696) drug.oru <- c(1.446,1.922,1.845,2.882) yaxis <- seq(1,4,by=1) plot(x=drug.or,y=yaxis,type='p',pch=17,xlim=c(0,3),axes=FALSE, xlab='Odds Ratio',ylab='',main='Reference Group: A only') axis(1,at=seq(0,3,by=0.5),labels=paste...

Hi all, I'm trying to add a X86 pattern to turn movl $-1, %eax into orl $-1, $eax I can't find a way to express this in TableGen syntax though. def : Pat<(set GR32:$src, (i32 -1)), (OR32ri8 GR32:$src, -1)>; results in an assertion about 'Unknown Node'. Joerg

...build/bin/clang -S -O2 1.c main: # @main # BB#0: subl $28, %esp leal 20(%esp), %eax movl %eax, 8(%esp) leal 24(%esp), %eax movl %eax, 4(%esp) movl $.L.str, (%esp) calll __isoc99_scanf movl 20(%esp), %eax * orl 24(%esp), %eax* addl $28, %esp retl As seen, optimization happened at IR level itself reflected in .s file. *GCC output for the same:* suyog at suyog-Inspiron-N5010:~$ gcc -S -O2 1.c main: .LFB23: .cfi_startproc pushl %ebp .cfi_def_cfa_offset 8 .cfi_offset 5, -8...

...1 file changed, 7 insertions(+) > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 08412f308de3..4622940134a5 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > orl $X86_CR4_LA57, %ecx > 1: > #endif > + > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE > + > + /* Early exception handling uses FSGSBASE on APs */ > + orl $X86_CR4_FSGSBASE, %ecx How is this supposed to work? Alternatives haven't r...

...1 file changed, 7 insertions(+) > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 08412f308de3..4622940134a5 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > orl $X86_CR4_LA57, %ecx > 1: > #endif > + > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE > + > + /* Early exception handling uses FSGSBASE on APs */ > + orl $X86_CR4_FSGSBASE, %ecx How is this supposed to work? Alternatives haven't r...

...0(%esp), %eax >>>> movl %eax, 8(%esp) >>>> leal 24(%esp), %eax >>>> movl %eax, 4(%esp) >>>> movl $.L.str, (%esp) >>>> calll __isoc99_scanf >>>> movl 20(%esp), %eax >>>> * orl 24(%esp), %eax* >>>> addl $28, %esp >>>> retl >>>> >>>> As seen, optimization happened at IR level itself reflected in .s file. >>>> >>>> *GCC output for the same:* >>>> >>>> suyog at suyog...

...know about ogg, and he needs time to encode his tracks to ogg, and then we should temporarily relay his mp3 stream, but we want to be dired by SC directory ... How to ? :-) -- ASPO Infog?rance http://aspo.rktmb.org/activites/infogerance Unofficial FAQ fcolc http://faq.fcolc.eu.org/ LUG sur Orl?ans et alentours. T?l : 02 38 76 43 65 (France)

...# @foo .cfi_startproc # BB#0: # %entry movb (%rdi), %al movzbl 1(%rdi), %ecx movb %al, z(%rip) movb %cl, z+1(%rip) incb %al shll $8, %ecx movzbl %al, %eax orl %ecx, %eax retq I was hoping it would do something along the lines of movb (%rdi), %al movb 1(%rdi), %ah movh %ax, z(%rip) incb %al retq Why is the x86 backend not getting this code? Does it know that AH:AL = AX? -Krzysztof -- Qualcomm Innovation Center, Inc....

...20(%esp), %eax >>>> movl %eax, 8(%esp) >>>> leal 24(%esp), %eax >>>> movl %eax, 4(%esp) >>>> movl $.L.str, (%esp) >>>> calll __isoc99_scanf >>>> movl 20(%esp), %eax >>>> orl 24(%esp), %eax >>>> addl $28, %esp >>>> retl >>>> >>>> As seen, optimization happened at IR level itself reflected in .s file. >>>> >>>> GCC output for the same: >>>> >>>> suyog at suyog-In...

...startproc ># BB#0: # %entry > movb (%rdi), %al > movzbl 1(%rdi), %ecx > movb %al, z(%rip) > movb %cl, z+1(%rip) > incb %al > shll $8, %ecx > movzbl %al, %eax > orl %ecx, %eax > retq > > >I was hoping it would do something along the lines of > > movb (%rdi), %al > movb 1(%rdi), %ah > movh %ax, z(%rip) > incb %al > retq > > >Why is the x86 backend not getting this code? Does it know that AH:AL = >...

On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote: > I'm trying to add a X86 pattern to turn > movl $-1, %eax > into > orl $-1, $eax Please make sure to measure the performance impact of doing this. You are creating a false dependency on the last instruction to write %eax, and the CPU won't be able to execute the following instructions in parallel. You may want to consider using xorl+decl instead. It is also thre...

...h/x86/kernel/head_64.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 08412f308de3..4622940134a5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) orl $X86_CR4_LA57, %ecx 1: #endif + + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE + + /* Early exception handling uses FSGSBASE on APs */ + orl $X86_CR4_FSGSBASE, %ecx + +.Lstartup_write_cr4: movq %rcx, %cr4 /* Setup early boot stage 4-/5-level pagetables...

...t; > > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > > index 08412f308de3..4622940134a5 100644 > > --- a/arch/x86/kernel/head_64.S > > +++ b/arch/x86/kernel/head_64.S > > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > > orl $X86_CR4_LA57, %ecx > > 1: > > #endif > > + > > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE > > + > > + /* Early exception handling uses FSGSBASE on APs */ > > + orl $X86_CR4_FSGSBASE, %ecx > > How is this...

Sorry, Forgot to say that I am looking for free software On Wed, 9 Mar 2005 16:31:10 +0100, Carsten Henkel <carsten@chatlabel.de> wrote: > Guten Tag Mohamed Eldesoky, > > Am Mittwoch, 9. M?rz 2005 um 16:19 schrieben Sie: > > ME> I want to do live streaming from the mic from windows machine. > ME> Which applications do you recommend ?? > > sam3

...e stopped working. Can anyone advise if there has been a change in how pickups work? Here is an example where 1000101 is trying to pick up a call to 1000103: <SIP/product-local-00000005>AGI Rx << EXEC Dial "Local/1000103 at product-pickup /n,60,M(product-answered^0^1306286740.11)orL(3600000:60000)" -- AGI Script Executing Application: (Dial) Options: (Local/1000103 at product-pickup /n,60,M(product-answered^0^1306286740.11)orL(3600000:60000)) > Limit Data for this call: > timelimit = 3600000 ms (3600.000 s) > play_warning = 60000 m...

...loggings on many computers from only one user? I have user who opened 12 computers, logged on those 12 computers and ran boinc-client on those 12 computers... I want to prevent this kind of behaviour... Thanks in advance. Regards. -- Olivier Pavilla << ????????????????>> S.C.I.R.C. Orl?ans (Bourgogne) - I.U.F.M. Centre-Val de Loire 72 Rue du Faubourg Bourgogne -45044 ORLEANS Cedex 1 Tel : 02-38-49-26-20 , mailto:olivier.pavilla at univ-orleans.fr http://blog.linux-squad.com - ??????? http://gallery.linux-squad.com - ??????? -------------- next part -------------- A non-text att...

Hello, Is it possible to have one password per source with Icecast 2.2.x ? How to ? -- ASPO Infog?rance http://aspo.rktmb.org/activites/infogerance Unofficial FAQ fcolc http://faq.fcolc.eu.org/ LUG sur Orl?ans et alentours (France). T?l : 02 34 08 26 04 / 06 33 26 13 14

Hi, All, Duncan, Rafael, David, Nick. This is regarding pattern matching in InstructionCombine pass. We use 'match' functions many times, but it doesn't do the pattern matching effectively. e.x. Lets take pattern : (A ^ B) | ((B ^ C) ^ A) -> (A ^ B) | C (B ^ A) | ((B ^ C) ^ A) -> (A ^ B) | C Both the patterns above are same, since ^ is commutative in Op0. But,

....cfi_startproc > # BB#0: # %entry > movb (%rdi), %al > movzbl 1(%rdi), %ecx > movb %al, z(%rip) > movb %cl, z+1(%rip) > incb %al > shll $8, %ecx > movzbl %al, %eax > orl %ecx, %eax > retq > > > I was hoping it would do something along the lines of > > movb (%rdi), %al > movb 1(%rdi), %ah > movh %ax, z(%rip) > incb %al > retq > > > Why is the x86 backend not getting this code? Try enabling the sub-register...