search for: krzysztof

Hello Krzysztof, The R_CASS definition is as follows: class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { let Namespace = "X86"; let HWEncoding = Enc; let SubRegs = subregs; } On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek < kparzysz...

Statically allocated array of pointed to hwmon_channel_info can be made const for safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org> --- This depends on hwmon core patch: https://lore.kernel.org/all/20230406203103.3011503-2-krzysztof.kozlowski at linaro.org/ Therefore I propose this should also go via hwmon tree. Cc: Jean Delvare <jdelvare at suse.com> Cc: Guenter Roe...

I don't remember the details of the particular case where we encountered this, but I think the loop started with the condition check and ended with an unconditional branch back to the beginning. -- Krzysztof Parzyszek  kparzysz at quicinc.com   LLVM compiler development -----Original Message----- From: Philip Reames <listmail at philipreames.com> Sent: Thursday, May 30, 2019 3:00 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com>; Finkel, Hal J. <hfinkel at anl.gov>; Kit Barton &l...

Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.i...

...if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || fatal error: too many errors emitted, stopping now [-ferror-limit=] 20 errors generated. When i comment out the line to construct 65536 bit register in registerinfo.td. it run fine. What to do? On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > Those couldn't be done generically, that's why the asserts were added. > > -Krzysztof > > On 7/19/2017 4:30 PM, Craig Topper wrote: > >> What about the static asserts protecting a Log call and another in the &gt...

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Hi Krzysztof, Krzysztof Parzyszek wrote: > On 10/18/2016 4:29 PM, Nuno Lopes wrote: >> Even %a and %b might not be the same in "%a = freeze(%x), %b = >> freeze(%x)" (each freeze returns an arbitrary, but fixed, value). > > Assume that %x is known to be a poison value and have: &g...

...GVN Hoist, I get: *x = 0 if (...) { ... = *x } else { ... = *x } That is, the store was hoisted above the loads. The code is not exactly public, so I can't just attach it as a testcase, but it seems like some simple check is missing somewhere. Does this ring a bell? -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

...with unsigned vs uint64_t. it looks as if i need to replace each occurrence of unsigned with uint64_t. Should i do it for complete llvm folder or codegen only?? i am continuously getting such errors which require changing unsigned with uint64_t. What to do now??? On Thu, Jul 20, 2017 at 1:03 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > It is possible that you have more than 64 lanes. In such case you would > need to reimplement LaneBitmask with a larger underlying type. Most of the > functionality is already localized to the header file, the only exception > may...

Mixed types aren't allowed. They are checked for in VerifySDNode in SelectionDAG.cpp and will fail an asserts build. ~Craig On Tue, Jul 7, 2020 at 8:25 AM Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > The problem can happen when you want to build a vector of i8, but i8 > itself is not legal on your target. All operands to BUILD_VECTOR will be > legalized to the next legal integer type, so you can end up with a > BU...

Hi, Just to clarify I am looking for a whole machine function analysis not just something restricted to within a machine basic block. Thanks. Regards, Venu. From: Raghavan, Venugopal Sent: Saturday, September 02, 2017 12:56 PM To: llvm-dev at lists.llvm.org Subject: Reaching definitions on Machine IR post register allocation Hi, Given a definition of a register by a machine instruction in

> On Jul 3, 2019, at 4:43 PM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > -----Original Message----- > From: David Greene <dag at cray.com> > Sent: Wednesday, July 3, 2019 2:44 PM > To: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > Cc: Krzysztof Parzyszek...

On Thu, Feb 20, 2020 at 10:48:33AM +0100, Jiri Slaby wrote: > On 19. 02. 20, 18:50, Krzysztof Kozlowski wrote: > > The ioreadX() helpers have inconsistent interface. On some architectures > > void *__iomem address argument is a pointer to const, on some not. > > > > Implementations of ioreadX() do not modify the memory under the address > > so they can be con...

Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes: > Vectorization must know the data layout: whether we have vectors (r1, > i1, r2, i2...) or (r1, r2, ...), (i1, i2, ...). These two approaches > are not compatible. If you have vector registers that can hold 8 > floats...

On 3/16/2016 12:36 PM, Krzysztof Parzyszek via llvm-dev wrote: > If the action is "Expand", which will convert the operation into Unfinished edit. Should be If the action is "Expand", the legalizer will replace the operation with... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aur...

Thanks for the clarification. The `except` seemed dangling to me, but it's early here. Just curious... how do we end up with a mixed type BUILD_VECTOR? That's counterintuitive. On Tue, Jul 7, 2020 at 10:58 AM Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Mixed integer types are ok, but the values will get truncated to the element type of the output value. It's pretty much what the comment says. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools de...

...on't need them? If AX was spilled in the middle of a live range of EAX, wouldn't restoring of AX need to implicitly define EAX? We deal with such cases a lot in the Hexagon backend and it continues to be a major pain. I'm trying to understand if there are better options for us. -Krzysztof On 5/24/2016 12:40 PM, Quentin Colombet wrote: > Hi Krzysztof, > >> On May 24, 2016, at 8:03 AM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> I'm trying to see how the x86 backend deals with the relationship between AL, AH and AX, b...

Doh. I missed the list in my first reply... Here's the replay of the conversation: ----- Renato: On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > --> %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR, > %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>, > %PC<imp-use,undef> > > Here the in...

Hi Krzysztof, freeze(poison) is different from undef today, in the sense that it is an instruction that produces some random, but fixed bit pattern. E.g. today in %x = undef %y = xor %x, %x we can fold %y to undef since each use of %x can independently see some arbitrary (up to the compiler / enviro...

I have the same issue, would it be easier and more useful to attach a flag to the instruction to tell the scheduler not to move instructions across this boundary? -Ryan On Tue, Nov 15, 2016 at 5:11 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > You can create a DAG mutation that adds artificial dependencies between A, > B and Z. > > -Krzysztof > > > On 11/15/2016 3:26 PM, Wei Ding via llvm-dev wrote: > >> Hello, >> >> I have a LL...