search for: krzysztof

Displaying 20 results from an estimated 1311 matches for "krzysztof".

2017 Jul 20
2
error:Ran out of lanemask bits to represent subregisterr
Hello Krzysztof, The R_CASS definition is as follows: class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { let Namespace = "X86"; let HWEncoding = Enc; let SubRegs = subregs; } On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek < kparzysz...
2019 May 30
4
Making loop guards part of canonical loop structure
I don't remember the details of the particular case where we encountered this, but I think the loop started with the condition check and ended with an unconditional branch back to the beginning. -- Krzysztof Parzyszek  kparzysz at quicinc.com   LLVM compiler development -----Original Message----- From: Philip Reames <listmail at philipreames.com> Sent: Thursday, May 30, 2019 3:00 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com>; Finkel, Hal J. <hfinkel at anl.gov>; Kit Barton &l...
2019 Sep 27
3
Question on target-features
Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.i...
2017 Jul 19
5
error:Ran out of lanemask bits to represent subregisterr
...if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || fatal error: too many errors emitted, stopping now [-ferror-limit=] 20 errors generated. When i comment out the line to construct 65536 bit register in registerinfo.td. it run fine. What to do? On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > Those couldn't be done generically, that's why the asserts were added. > > -Krzysztof > > On 7/19/2017 4:30 PM, Craig Topper wrote: > >> What about the static asserts protecting a Log call and another in...
2016 Oct 20
3
RFC: Killing undef and spreading poison
Hi Krzysztof, Krzysztof Parzyszek wrote: > On 10/18/2016 4:29 PM, Nuno Lopes wrote: >> Even %a and %b might not be the same in "%a = freeze(%x), %b = >> freeze(%x)" (each freeze returns an arbitrary, but fixed, value). > > Assume that %x is known to be a poison value and...
2016 Apr 28
2
Assertion in MachineScheduler.cpp
On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
2016 Aug 05
3
GVN Hoist moving a store across load
...GVN Hoist, I get: *x = 0 if (...) { ... = *x } else { ... = *x } That is, the store was hoisted above the loads. The code is not exactly public, so I can't just attach it as a testcase, but it seems like some simple check is missing somewhere. Does this ring a bell? -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
2017 Jul 19
2
error:Ran out of lanemask bits to represent subregisterr
...with unsigned vs uint64_t. it looks as if i need to replace each occurrence of unsigned with uint64_t. Should i do it for complete llvm folder or codegen only?? i am continuously getting such errors which require changing unsigned with uint64_t. What to do now??? On Thu, Jul 20, 2017 at 1:03 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > It is possible that you have more than 64 lanes. In such case you would > need to reimplement LaneBitmask with a larger underlying type. Most of the > functionality is already localized to the header file, the only exception > may...
2020 Jul 07
2
BUILD_VECTOR disambiguation
Mixed types aren't allowed. They are checked for in VerifySDNode in SelectionDAG.cpp and will fail an asserts build. ~Craig On Tue, Jul 7, 2020 at 8:25 AM Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > The problem can happen when you want to build a vector of i8, but i8 > itself is not legal on your target. All operands to BUILD_VECTOR will be > legalized to the next legal integer type, so you can end up with a > BU...
2017 Sep 04
7
Reaching definitions on Machine IR post register allocation
Hi, Just to clarify I am looking for a whole machine function analysis not just something restricted to within a machine basic block. Thanks. Regards, Venu. From: Raghavan, Venugopal Sent: Saturday, September 02, 2017 12:56 PM To: llvm-dev at lists.llvm.org Subject: Reaching definitions on Machine IR post register allocation Hi, Given a definition of a register by a machine instruction in
2020 Feb 24
3
[RESEND PATCH v2 9/9] ath5k: Constify ioreadX() iomem argument (as in generic implementation)
On Thu, Feb 20, 2020 at 10:48:33AM +0100, Jiri Slaby wrote: > On 19. 02. 20, 18:50, Krzysztof Kozlowski wrote: > > The ioreadX() helpers have inconsistent interface. On some architectures > > void *__iomem address argument is a pointer to const, on some not. > > > > Implementations of ioreadX() do not modify the memory under the address > > so they can be con...
2019 Jul 04
3
RFC: Complex in LLVM
> On Jul 3, 2019, at 4:43 PM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > -----Original Message----- > From: David Greene <dag at cray.com> > Sent: Wednesday, July 3, 2019 2:44 PM > To: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > Cc: Krzysztof Parzyszek...
2019 Jul 03
3
RFC: Complex in LLVM
Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes: > Vectorization must know the data layout: whether we have vectors (r1, > i1, r2, i2...) or (r1, r2, ...), (i1, i2, ...). These two approaches > are not compatible. If you have vector registers that can hold 8 > floats...
2016 May 24
3
Liveness of AL, AH and AX in x86 backend
...on't need them? If AX was spilled in the middle of a live range of EAX, wouldn't restoring of AX need to implicitly define EAX? We deal with such cases a lot in the Hexagon backend and it continues to be a major pain. I'm trying to understand if there are better options for us. -Krzysztof On 5/24/2016 12:40 PM, Quentin Colombet wrote: > Hi Krzysztof, > >> On May 24, 2016, at 8:03 AM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> I'm trying to see how the x86 backend deals with the relationship between AL, AH a...
2015 Aug 12
2
ARM: Predicated returns considered analyzable?
Doh. I missed the list in my first reply... Here's the replay of the conversation: ----- Renato: On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > --> %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR, > %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>, > %PC<imp-use,undef> > > Here the in...
2020 Jul 07
3
BUILD_VECTOR disambiguation
Thanks for the clarification. The `except` seemed dangling to me, but it's early here. Just curious... how do we end up with a mixed type BUILD_VECTOR? That's counterintuitive. On Tue, Jul 7, 2020 at 10:58 AM Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Mixed integer types are ok, but the values will get truncated to the element type of the output value. It's pretty much what the comment says. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools de...
2016 Nov 15
5
how to prevent LLVM back-end from reordering instructions at instruction scheduling?
I have the same issue, would it be easier and more useful to attach a flag to the instruction to tell the scheduler not to move instructions across this boundary? -Ryan On Tue, Nov 15, 2016 at 5:11 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > You can create a DAG mutation that adds artificial dependencies between A, > B and Z. > > -Krzysztof > > > On 11/15/2016 3:26 PM, Wei Ding via llvm-dev wrote: > >> Hello, >> >> I h...
2016 Oct 18
7
RFC: Killing undef and spreading poison
Hi Krzysztof, freeze(poison) is different from undef today, in the sense that it is an instruction that produces some random, but fixed bit pattern. E.g. today in %x = undef %y = xor %x, %x we can fold %y to undef since each use of %x can independently see some arbitrary (up to the compiler / en...
2016 Mar 16
2
how to type-legalize a dag
On 3/16/2016 12:36 PM, Krzysztof Parzyszek via llvm-dev wrote: > If the action is "Expand", which will convert the operation into Unfinished edit. Should be If the action is "Expand", the legalizer will replace the operation with... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aur...
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
...appens, though. In this case, the entire bb.2 will be used as the new tail leaving us without a good point to put the implicit def at. In this particular testcase, the implicit def could go in bb.0 (which was not involved in the tail merging at all), but in general that may not be an option. -Krzysztof On 7/27/2017 2:20 PM, Quentin Colombet wrote: > Yeah, that’s want I was expecting from the verifier. > I’d say we should add an implicit_def (assuming it gets kill at code emission) in the part where it is undef. > >> On Jul 27, 2017, at 11:52 AM, Krzysztof Parzyszek <...