Rail Shafigulin via llvm-dev
2015-Nov-12 00:34 UTC
[llvm-dev] Way to specify instruction latency in itinerary scheduling model
Does anybody know how to specify instruction latency in the itinerary scheduling model? For some reason no matter what I do I get a latency of 1. -- Rail -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151111/161bd6cb/attachment.html>
Hal Finkel via llvm-dev
2015-Nov-12 05:45 UTC
[llvm-dev] Way to specify instruction latency in itinerary scheduling model
----- Original Message -----> From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Wednesday, November 11, 2015 6:34:03 PM > Subject: [llvm-dev] Way to specify instruction latency in itinerary scheduling model > > Does anybody know how to specify instruction latency in the itinerary > scheduling model? For some reason no matter what I do I get a > latency of 1. >I suspect this is because you're specifying the pipeline structure but not the latencies. For example: InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>], [72, 0, 0]>, The '[InstrStage<1, [A2_FU]>]' specifies the pipeline structure (or, here, the first stage of the pipeline), and the '[72, 0, 0]' specifies the operand latencies (output on cycle 72, reads on cycle 0). -Hal> > -- > > Rail > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-- Hal Finkel Assistant Computational Scientist Leadership Computing Facility Argonne National Laboratory
Rail Shafigulin via llvm-dev
2015-Nov-12 17:02 UTC
[llvm-dev] Way to specify instruction latency in itinerary scheduling model
> > I suspect this is because you're specifying the pipeline structure but not > the latencies. For example: > > InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>], > [72, 0, 0]>, > > The '[InstrStage<1, [A2_FU]>]' specifies the pipeline structure (or, here, > the first stage of the pipeline), and the '[72, 0, 0]' specifies the > operand latencies (output on cycle 72, reads on cycle 0). > > -Hal > > -- > Hal Finkel > Assistant Computational Scientist > Leadership Computing Facility > Argonne National Laboratory >I see. Thank you. -- R -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151112/084a1a06/attachment.html>