search for: scheduling

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that describes the new MI s...

Hi, I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to include in our paper some brief descriptions of the two LLVM schedulers that we are comparing a...

...faster than (2) by 10%. We concluded that adding precise latency information may significantly improve the performance of programs like gromacs, which have a high degree of ILP. However, we did not do any performance analysis to verify that the performance improvement is indeed due to improving ILP scheduling (reducing pipeline stalls) not due to some other factor, such as memory performance, which may have gotten coincidentally improved by the reordering. We are not currently running any performance analysis tools, but if you are interested, we can identify the code section whose reordering has led t...

...er a year ago, and the release of 3.3. The biggest change was loop vectorization, which reduces register pressure and somewhat preschedules loops. Since 3.3 was released, the generic MI scheduler's heuristics were reevaluated in preparation for making it the default for targets without a custom scheduling strategy--more on that later. The source order scheduler was also fixed so that it actually preserves IR order, which is at least closer to source order. For many benchmarks we've looked at, source order scheduling approaches the lower bound on register pressure--heuristics can only hurt--maki...

...gt; want to use the new scheduler before it is mature, you'll need to > >> follow trunk. > > > > Ok, but that doesn't answer the question. Is SchedulerDAG going > > away? If so, what's the timeframe for that? 3.2? > > SchedulerDAG is used for both SD scheduling and MI scheduling. It's > not going away. > > SD scheduling is not going away in 3.2--it will be the first release > with MI scheduling on by default. > > If all goes well, I expect SD scheduling to be removed by 3.3. That > has not been discussed. > > Consider thi...

On Sep 17, 2011, at 10:07 AM, Ghassan Shobaki wrote: > Hi, > > I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to include in our paper some brief descriptions of the two LLVM schedulers that we are comparing again...

Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that describes the new MI sche...

...uly 1, 2013 8:10 PM Subject: Re: MI Scheduler vs SD Scheduler? Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: Hi, > > >We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that describes the new MI s...

...faster than (2) by 10%. We concluded that adding precise latency information may significantly improve the performance of programs like gromacs, which have a high degree of ILP. However, we did not do any performance analysis to verify that the performance improvement is indeed due to improving ILP scheduling (reducing pipeline stalls) not due to some other factor, such as memory performance, which may have gotten coincidentally improved by the reordering. Thanks for the clear explanation. How much of LLVM's existing scheduler framework do you use? Do you schedule the selection DAG? Are  you using...

...faster than (2) by 10%. We concluded that adding precise latency information may significantly improve the performance of programs like gromacs, which have a high degree of ILP. However, we did not do any performance analysis to verify that the performance improvement is indeed due to improving ILP scheduling (reducing pipeline stalls) not due to some other factor, such as memory performance, which may have gotten coincidentally improved by the reordering. Thanks for the clear explanation. How much of LLVM's existing scheduler framework do you use? Do you schedule the selection DAG? Are you using...

On May 10, 2012, at 9:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> - Target pass configuration: DONE >> - MachineScheduler pass framework: DONE >> - MI Scheduling DAG: DONE >> - AliasAnalysis aware DAG option: In review (Sergei) >> - Bidirectional list scheduling: DONE >> - LiveInterval Update: WIP (simple instruction reordering is >> supported) >> - Target-independent precise modeling of register pressure: DONE >> - Regis...

If a sched job depends on a dma-fence from a job from the same GPU scheduler instance, but a different scheduler entity, the GPU scheduler does only wait for the particular job to be scheduled, rather than for the job to fully complete. This is due to the GPU scheduler assuming that there is a scheduler instance per ring. However, the current implementation, in order to avoid arbitrary amounts of

Hi all, After many days of struggling, I have a multi-model form with ajax elements more or less working, but I''m hitting a wall with a few bugs that I can''t figure out. Guidance would be very much appreciated. I''m using the Ryan Bates technique from Advanced Rails recipes to dynamically add and remove elements on a multi-model form.

...iterations   Most of the above performance differences have been correlated with significant changes in spill counts in hot functions. Note that the ILP scheduler causes a degradation of 22% on one benchmark (lbm) relative to the source scheduler. We have verified that this happens because of poor scheduling that increases the register pressure and thus leads to generating excessive spills in this benchmark’s hottest loop. We should probably report this as a performance bug if ILP stays the default scheduler on x86-64. Regards Ghassan Shobaki Assistant Professor  Department of Computer Science  Princ...

Hi, We are currently working on revising a journal article that describes our work on pre-allocation scheduling using LLVM and have some questions about LLVM's pre-allocation scheduler. The answers to these question will help us better document and analyze the results of our benchmark tests that compare our algorithm with LLVM's pre-allocation scheduling algorithm. First, here is a brief description...

On Sep 29, 2012, at 2:43 AM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently working on revising a journal article that describes our work on pre-allocation scheduling using LLVM and have some questions about LLVM's pre-allocation scheduler. The answers to these question will help us better document and analyze the results of our benchmark tests that compare our algorithm with LLVM's pre-allocation scheduling algorithm. > > First, here is a brief d...

...e now? -Dilan On Mon, Jul 31, 2017 at 3:24 PM Matthias Braun <mbraun at apple.com> wrote: > > > On Jul 31, 2017, at 2:51 PM, Dilan Manatunga via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > I was looking into how SelectionDAG scheduling is done in LLVM for > different backends, and I noticed that for the X86 backend, even though it > sets scheduling preferences of ILP or RegisterPressure depending on > architecture, in the end, it ends up using source scheduling. I realized > this is because it overrides enableMachineS...

My 2c... Even though I understand it might be way off in the future, but we are talking about long term plans here anyway. Also as a VLIW backend maintainer, I just have to say it :) - We do need to have a way to assign bundles much earlier than we do now. And it needs to be intertwined with scheduling (Bundler currently reuses a good chunk of scheduler infrastructure). It is also obvious that it will have adverse effect on all the downstream passes. It is further insulting due to the fact that bundling is trivial to do during scheduling, but it goes hard against the original assumptions made els...

...ment that we have seen is 3% on the Gromacs benchmark. Is this consistent with your test results? I haven’t benchmarked fortran. On x86-64, I regularly see wild swings in performance, 10-20% for small codegen changes (small benchmarks with a primary hot loop). This is not a natural consequence of scheduling, unless spill code changed in the hot loop (rare on x86-64). Quite often, a somewhat random change in copy coalescing results in different register allocation and code layout. The results are chaotic and very platform (linker) and microarchitecture specific. Large benchmarks are immune to wild swin...

...used in the block.I assume that he meant that registers that are live-through (both live-in and live-out) are not accounted for in register pressure calculations. If a register is either live-in or live-out but not both, it must be accounted for, because its live range length may be affected by the scheduling decisions within the region. I understand that the live range of a live-through register is not affected by the scheduling decisions within the region, but unfortunately, the scheduler that we are integrating in the machine scheduler does need to know the absolute register pressure. Our scheduler...