llvm dev - Aug 2014 - [LLVMdev] Pseudo load and store instructions for AArch64

Hello,

I'm trying to add pseudo 64-bit load and store instructions for AArch64,
which
should have latencies set to "1" while being otherwise exactly the
same as
normal load and store instructions.  Various assertions fire (even different
ones for the same binary, maybe something is uninitialized) and I can't
understand what's wrong.  Related pieces added by me:

to AArch64InstrInfo.td:

  let isReMaterializable = 1 in {
    def FakeLoad64 : Pseudo<(outs GPR64:$Rt), (ins GPR64sp:$Rn, GPR32:$Rm,
ro_Wextend64:$extend), []>;
    def FakeStore64 : Pseudo<(outs), (ins GPR64:$Rt, GPR64sp:$Rn, GPR32:$Rm,
ro_Wextend64:$extend), []>;
  }

  def AArch64fakeload64 : SDNode<"AArch64ISD::FakeLoad64",
SDTIntBinOp, [SDNPHasChain]>;
  def AArch64fakestore64 : SDNode<"AArch64ISD::FakeStore64",
SDTIntBinOp, [SDNPHasChain]>;

to AArch64ISD in AArch64ISelLowering.h below ISD::FIRST_TARGET_MEMORY_OPCODE:

  FakeLoad64,
  FakeStore64

in AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy():

  SmallVector<SDValue, 4> Ops;
  Ops.push_back(Chain);
  Ops.push_back(DAG.getNode(ISD::ADD, dl, MVT::i64, Src,
                            DAG.getConstant(SrcOff, MVT::i64)));
  // Ops.push_back(SrcPtrInfo.getWithOffset(SrcOff));
  Ops.push_back(DAG.getConstant(0, MVT::i64));

  Loads[i] = DAG.getNode(AArch64::FakeLoad64, dl, VT, Ops);

There seems to be something wrong with pointer information inside getNode() as
llvm::MachinePointerInfo::getAddrSpace() asserts.

I can't find an example of similar instructions to start with, are there any
similar pseudoes already?

Any help would be appreciated, even if someone could confirm that it should
be possible to do and I'm just missing something.

Thanks,
Sergey

On 13 August 2014 15:46, Sergey Dmitrouk <sdmitrouk at accesssoftek.com>
wrote:
> I'm trying to add pseudo 64-bit load and store instructions for
AArch64, which
> should have latencies set to "1" while being otherwise exactly
the same as
> normal load and store instructions.
Hi Sergey,

Can I ask why would you need that?

> There seems to be something wrong with pointer information inside getNode()
as
> llvm::MachinePointerInfo::getAddrSpace() asserts.
Looks like there's specific knowledge about the types and instructions
codes in switches midway through that is not recognizing your new
pseudos.

One way to find them out is to grep for the instruction codes yours is
similar to, and then see if you need to add your pseudos

cheers,
--renato

Hi Renato,
> > I'm trying to add pseudo 64-bit load and store instructions for
AArch64, which
> > should have latencies set to "1" while being otherwise
exactly the same as
> > normal load and store instructions.
> 
> Can I ask why would you need that?
This is the only way I found to stop Machine Instruction Scheduler from
reordering load and store instructions.  I asked on this specific topic
several times before, but no one answered.  The following approaches
didn't work in this case:

 - different kind of chaining;
 - gluing;
 - single pseudo instruction for load and store as it needs temporary
   register, but such pseudos are expanded after RA.

It's needed to make code of inlined memcpy() more efficient.
> Looks like there's specific knowledge about the types and instructions
> codes in switches midway through that is not recognizing your new
> pseudos.
>
> One way to find them out is to grep for the instruction codes yours is
> similar to, and then see if you need to add your pseudos
Thanks, I'll try that.

Regards,
Sergey