Displaying 20 results from an estimated 100 matches similar to: "[LLVMdev] Pseudo load and store instructions for AArch64"
2019 Sep 10
2
tablegen exponential behavior
Hi,
I implemented a pattern matching of the dot product for arm64
and it seemed to work well for the basic case, i.e.,
class mulB<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn, node:$Rm, node:$offset),
(mul (ldop (add node:$Rn, node:$offset)),
(ldop (add node:$Rm, node:$offset)))>;
class mulBz<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn,
2007 Apr 18
0
[RFC/PATCH LGUEST X86_64 09/13] lguest64 devices
plain text document attachment (lguest64-device.patch)
We started working a little bit on the devices for lguest64.
This is still very much a work-in-progress and needs much more work.
Signed-off-by: Steven Rostedt <srostedt@redhat.com>
Signed-off-by: Glauber de Oliveira Costa <glommer@gmail.com>
Cc: Chris Wright <chrisw@sous-sol.org>
Index:
2007 Apr 18
0
[RFC/PATCH LGUEST X86_64 09/13] lguest64 devices
plain text document attachment (lguest64-device.patch)
We started working a little bit on the devices for lguest64.
This is still very much a work-in-progress and needs much more work.
Signed-off-by: Steven Rostedt <srostedt@redhat.com>
Signed-off-by: Glauber de Oliveira Costa <glommer@gmail.com>
Cc: Chris Wright <chrisw@sous-sol.org>
Index:
2015 Dec 01
3
Endianness for multi-word types
On 1 December 2015 at 13:41, Tim Shen via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> As a simple solution, when see a LLVM IR bitcast, instead of generating
> (ISD::BITCAST x), can we generate (exchange_hi_lo (ISD::BITCAST x)) instead?
An LLVM bitcast is defined to be equivalent to a store/load pair.
Changing that for ISD::BITCAST would be very surprising, and I
wouldn't
2018 Dec 05
2
Strange regalloc behaviour: one more available register causes much worse allocation
Preamble
--------
While working on an IR-level optimisation completely unrelated to register
allocation I happened to trigger some really strange register allocator
behaviour causing a large regression in bzip2 in spec2006. I've been trying
to fix that regression before getting the optimisation patch committed, because
I don't want to regress spec2006, but I'm basically fumbling in
2018 Dec 05
3
Strange regalloc behaviour: one more available register causes much worse allocation
enableAdvancedRASplitCost() does the same thing as ConsiderLocalIntervalCost, but as a
subtarget option instead of a command-line option, and as I’ve said it doesn’t help because
it’s a non-local interval causing the eviction chain (RAGreedy::splitCanCauseEvictionChain
only considers the local interval for a single block, and it’s unclear to me how to make it
handle a non-local interval).
John
2007 May 09
1
[patch 3/9] lguest: the host code
From: Rusty Russell <rusty@rustcorp.com.au>
This is the code for the "lg.ko" module, which allows lguest guests to
be launched.
[akpm@linux-foundation.org: update for futex-new-private-futexes]
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Cc: Andi Kleen <ak@suse.de>
Cc: Eric Dumazet <dada1@cosmosbay.com>
Signed-off-by: Andrew Morton
2007 May 09
1
[patch 3/9] lguest: the host code
From: Rusty Russell <rusty@rustcorp.com.au>
This is the code for the "lg.ko" module, which allows lguest guests to
be launched.
[akpm@linux-foundation.org: update for futex-new-private-futexes]
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Cc: Andi Kleen <ak@suse.de>
Cc: Eric Dumazet <dada1@cosmosbay.com>
Signed-off-by: Andrew Morton
2016 Feb 23
2
[PPC] Linker fails on -fstack-protector
On Mon, Feb 22, 2016 at 5:00 PM Eric Christopher <echristo at gmail.com> wrote:
> Yeah, for most of the architectures listed there it's not particularly
> useful as they support direct access to TLS variables (as Joerg says
> later). That grep isn't representative of how the data is actually
> accessed. If the current address space way of specifying isn't doable on
2013 Sep 25
1
[LLVMdev] arm64 / iOS support
Attached is a working patch set for llvm to be able to emit arm64
(currently as triple aarch64-apple-ios) mach-o object files, in case
someone is interested. I'm not sure if the llvm maintainers want the
patch given the previous message that there's going to be an official
patch set from apple to support this, but here is mine.
What works (tested on an iPhone 5S):
* objc strings,
2018 Apr 30
0
[SelectionDAG] DbgValue nodes aren't transferred
Hi Jonas,
I have another case that DBG_VALUE is not produced. I would appreciate it if you could take a quick look at the testcase below.
test code:
llc -mtriple=aarch64 -stop-after=livedebugvalues -o - test.ll
; Function Attrs: nounwind ssp uwtable
define void @f() #0 !dbg !4 {
entry:
tail call void @h(i16 0) #2, !dbg !14
%call = tail call i16 (...) @g() #2, !dbg !15
tail call void
2019 Sep 27
4
Dealing with boolean values in GlobalISel
Hi,
I’ve been thinking about what the strategy to use for boolean values in GlobalISel. There are a few semantic and mechanical issues I’ve encountered.
For background, on AMDGPU, there are two kinds of bool/s1 values. Contextually, a real boolean value will either be a 1-bit scalar condition (in a non-allocatable physical condition register, which will need to be copied to an allocatable class
2018 Apr 30
0
[SelectionDAG] DbgValue nodes aren't transferred
Thanks! It looks like SelectionDAG::salvageDebugInfo handles only addition with constant.
Sejong
From: aprantl at apple.com <aprantl at apple.com>
Sent: Monday, April 30, 2018 1:53 PM
To: Se Jong Oh <sejooh at microsoft.com>
Cc: jdevlieghere at apple.com; Vedant Kumar <vsk at apple.com>; llvm-dev at lists.llvm.org; pidgeot18 at gmail.com
Subject: Re: [llvm-dev] [SelectionDAG]
2018 Apr 30
2
[SelectionDAG] DbgValue nodes aren't transferred
> On Apr 30, 2018, at 1:49 PM, Se Jong Oh <sejooh at microsoft.com> wrote:
>
> Hi Jonas,
>
> I have another case that DBG_VALUE is not produced. I would appreciate it if you could take a quick look at the testcase below.
>
>
> test code:
>
> llc -mtriple=aarch64 -stop-after=livedebugvalues -o - test.ll
>
> ; Function Attrs: nounwind ssp uwtable
>
2020 Jun 15
2
[AArch64][SVE] Floating Point Code Gen
Hello,
I am following up on the issue discussed at the SVE meeting, Sander
mentioned that there were some patterns missing from SVE CodeGen for
floating point operations, but I was unable to identify them.
He mentioned something about looking at the ISelLowering for AArch64 to
identify them, so if there is any information of that regard it would be
greatly appreciated so we can contribute with
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
In the RISC-V V extension, there is no upper limit to the size vector
registers can be in a future CPU. (Formally, the upper limit is at
least 2^31 bytes)
Generic code can enquire the size, dynamically allocate space, and
transparently save and restore the contents of a vector register or
registers.
On Fri, May 24, 2019 at 11:28 AM JinGu Kang via llvm-dev
<llvm-dev at lists.llvm.org>
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
JinGu:
I’m not Graham, but you might find the following link a good starting point.
https://community.arm.com/developer/tools-software/hpc/b/hpc-blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture
The question you ask doesn’t have a short answer. The compiler and the instruction set design work together to allow programs to be compiled without knowing
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi All,
I have read the links from Joel. It seems one of its main focus is vectorization of loop with vector predicate register. I am not sure we need the scalable vector type for it. Let's see a simple example from the white paper.
1 void example01(int *restrict a, const int *b, const int *c, long N)
2 {
3 long i;
4 for (i = 0; i < N; ++i)
5 a[i] = b[i] + c[i];
6 }
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi,
Are there any objections to going ahead with this? If not, we'll try to get the patches reviewed and committed after the 7.0 branch occurs.
-Graham
> On 2 Jul 2018, at 10:53, Graham Hunter <Graham.Hunter at arm.com> wrote:
>
> Hi,
>
> I've updated the RFC slightly based on the discussion within the thread, reposted below. Let me know if I've missed
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi Graham,
Thanks for your kind explanation.
There was internal discussion about it. If possible, can you let me know the Clang/LLVM CodeGen patches for the vector type on phabricator please? I would like to check what kinds of the restrictions the type causes on Clang/LLVM.
Thanks,
JinGu Kang
________________________________
From: Graham Hunter <Graham.Hunter at arm.com>
Sent: 28 May