search for: aarch64isd

...efined to be equivalent to a store/load pair. Changing that for ISD::BITCAST would be very surprising, and I wouldn't recommend it. It's a very useful invariant for reasoning about what should happen. When we had to work around similar endian nightmares in ARM I think we ended up creating AArch64ISD::NVCAST to represent a true nop cast. Cheers. Tim.

Hello, I am following up on the issue discussed at the SVE meeting, Sander mentioned that there were some patterns missing from SVE CodeGen for floating point operations, but I was unable to identify them. He mentioned something about looking at the ISelLowering for AArch64 to identify them, so if there is any information of that regard it would be greatly appreciated so we can contribute with

...let isReMaterializable = 1 in { def FakeLoad64 : Pseudo<(outs GPR64:$Rt), (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), []>; def FakeStore64 : Pseudo<(outs), (ins GPR64:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), []>; } def AArch64fakeload64 : SDNode<"AArch64ISD::FakeLoad64", SDTIntBinOp, [SDNPHasChain]>; def AArch64fakestore64 : SDNode<"AArch64ISD::FakeStore64", SDTIntBinOp, [SDNPHasChain]>; to AArch64ISD in AArch64ISelLowering.h below ISD::FIRST_TARGET_MEMORY_OPCODE: FakeLoad64, FakeStore64 in AArch64SelectionDAGInfo::Emi...

...t2: i32,ch = CopyFromReg t0, Register:i32 %0 t14: i32 = and t2, Constant:i32<1> t4: i32,ch = CopyFromReg t0, Register:i32 %1 t6: i32,ch = CopyFromReg t0, Register:i32 %2 t8: i32 = select t14, t4, t6 t10: ch,glue = CopyToReg t0, Register:i32 $w0, t8 t11: ch = AArch64ISD::RET_FLAG t10, Register:i32 $w0, t10:1 Such that the selector doesn’t need to worry about the edge case of a non-boolean s1 value. Can we make truncates to s1 illegal? The documentation currently states it must be legal for all result types for a legal source type, and is a no-op bit operation to...

...s of the stack local load > rather than an offset from an address space. > I also found a similar case - getSafeStackPointerLocation(). On X86 it's implemented in terms of address space (similar to getStackCooikeLocation), but on AArch64 it's implemented in terms of a target specific AArch64ISD::THREAD_POINTER and Intrinsic::aarch64_thread_pointer. To make the fix least surprising, I can either do: 1) Create PPCISD::THREAD_POINTER and Intrinsic::ppc_thread_pointer and do similar things aarch64 does; or 2) Don't create PPCISD::THREAD_POINTER, but directly calls llvm.read_register intr...

...values. > > ================== > 5. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::DUP. > > GlobalISel > ---------- > > Since GlobalISel was enabled by default on AArch64, it was necessary to add > scalable vector support...

...; `` > > ================== > 6. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::DUP. > > GlobalISel > ---------- > > Since GlobalISel was enabled by default on AArch64, it was necessary to add > scalable vector suppo...

...tail call i16 (...) @g() #2, !dbg !15 tail call void @llvm.dbg.value(metadata i16 %call, metadata !8, metadata !16), !dbg !17 tail call void @h(i16 %call) #2, !dbg !18 ret void, !dbg !19 } For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0. t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11 t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11 t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, test.c:5:11 Then, TargetLowerin...

...l need to find new ways to recognize and fold these values. ================== 5. Code Generation ================== IR splats will be converted to an experimental splatvector intrinsic in SelectionDAGBuilder. All three intrinsics are custom lowered and legalized in the AArch64 backend. Two new AArch64ISD nodes have been added to represent the same concepts at the SelectionDAG level, while splatvector maps onto the existing AArch64ISD::DUP. GlobalISel ---------- Since GlobalISel was enabled by default on AArch64, it was necessary to add scalable vector support to the LowLevelType implementation. A...

I found a bit weird to use address space for this, since the offset of getting stack_guard in TCB is, unfortunately, negative: https://github.com/gcc-mirror/gcc/blob/master/gcc/config/rs6000/linux64.h#L610 In my understanding an address space is referring to a segment register (-on powerpc 32bit; or SLB entry on powerpc 64bit?) with a non-negative offset value, so that it's actually accessing

...l need to find new ways to recognize and fold these values. ================== 5. Code Generation ================== IR splats will be converted to an experimental splatvector intrinsic in SelectionDAGBuilder. All three intrinsics are custom lowered and legalized in the AArch64 backend. Two new AArch64ISD nodes have been added to represent the same concepts at the SelectionDAG level, while splatvector maps onto the existing AArch64ISD::DUP. GlobalISel ---------- Since GlobalISel was enabled by default on AArch64, it was necessary to add scalable vector support to the LowLevelType implementation. A...

...5 > tail call void @llvm.dbg.value(metadata i16 %call, metadata !8, metadata !16), !dbg !17 > tail call void @h(i16 %call) #2, !dbg !18 > ret void, !dbg !19 > } > > For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0. > > t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11 > t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11 > t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, test.c:5:11 > > T...

> On Mar 14, 2018, at 7:55 PM, Se Jong Oh <sejooh at microsoft.com> wrote: > > Hi Jonas, > > Thanks for taking a look! It makes linear-dbg-value.ll pass for my target by producing DEBUG_VALUEs correctly. I also tried a simple function with few operations and confirmed DEBUG_VALUEs which are not produced without trasferDbgValues in SetPromotedInteger. That’s great news! Do

...Reloc::Static) { + // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate + // to zero when they remain undefined. In PIC mode the GOT can take care of + // this, but in absolute mode we use a constant pool load. + SDValue PoolAddr; + PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT, + DAG.getTargetConstantPool(GV, PtrVT, 0, 0, + AArch64II::MO_NO_FLAG), + DAG.getTargetConstantPool(GV, PtrVT, 0, 0, +...

...l need to find new ways to recognize and fold these values. ================== 5. Code Generation ================== IR splats will be converted to an experimental splatvector intrinsic in SelectionDAGBuilder. All three intrinsics are custom lowered and legalized in the AArch64 backend. Two new AArch64ISD nodes have been added to represent the same concepts at the SelectionDAG level, while splatvector maps onto the existing AArch64ISD::DUP. GlobalISel ---------- Since GlobalISel was enabled by default on AArch64, it was necessary to add scalable vector support to the LowLevelType implementation. A...

...values. > > ================== > 5. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::DUP. > > GlobalISel > ---------- > > Since GlobalISel was enabled by default on AArch64, it was necessary to add > scalable vector support...

...==== > > > > IR splats will be converted to an experimental splatvector > intrinsic in > > SelectionDAGBuilder. > > > > All three intrinsics are custom lowered and legalized in the > AArch64 backend. > > > > Two new AArch64ISD nodes have been added to represent the same > concepts > > at the SelectionDAG level, while splatvector maps onto the existing > > AArch64ISD::DUP. > > > > GlobalISel > > ---------- > > > > Since GlobalISel was enabled by...

> -----Original Message----- > From: Hal Finkel [mailto:hfinkel at anl.gov] > Sent: Tuesday, December 01, 2015 1:01 AM > To: Tim Shen > Cc: Gao, Yunzhong; llvm-dev at lists.llvm.org; Kit Barton; Nemanja Ivanovic > Subject: Re: [llvm-dev] Endianness for multi-word types > > ----- Original Message ----- > > From: "Tim Shen via llvm-dev" <llvm-dev at

...l = tail call i16 (...) @g() #2, !dbg !15 tail call void @llvm.dbg.value(metadata i16 %call, metadata !8, metadata !16), !dbg !17 tail call void @h(i16 %call) #2, !dbg !18 ret void, !dbg !19 } For the second call, the AArch64 ISel lowering produces a 32-bit CopyFromReg from w0. t18: ch,glue = AArch64ISD::CALL t15, TargetGlobalAddress:i64<i16 (...)* @g> 0, RegisterMask:Untyped, test.c:5:11 t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1, test.c:5:11 t20: i32,ch,glue = CopyFromReg t19, Register:i32 $w0, t19:1, test.c:5:11 Then, TargetLowering:...

...> `` > > ================== > 6. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::DUP. > > GlobalISel > ---------- > > Since GlobalISel was enabled by default on AArch64, it was necessary to add > scalable vector support...