Displaying 4 results from an estimated 4 matches for "gpr64sp".
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gpr64
2019 Sep 10
2
tablegen exponential behavior
...(ldop (add node:$Rm, node:$offset)))>;
class mulBz<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn, node:$Rm),
(mul (ldop node:$Rn), (ldop node:$Rm))>;
class DotProductI32<Instruction DOT, SDPatternOperator ldop> :
Pat<(i32 (add (mulB<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 3)),
(add (mulB<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 2)),
(add (mulB<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 1)),
(mulBz<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))),
(EXTRACT_SUBREG
(i64 (DOT (DUPv2i32gpr WZR),...
2014 Aug 13
2
[LLVMdev] Pseudo load and store instructions for AArch64
...tructions. Various assertions fire (even different
ones for the same binary, maybe something is uninitialized) and I can't
understand what's wrong. Related pieces added by me:
to AArch64InstrInfo.td:
let isReMaterializable = 1 in {
def FakeLoad64 : Pseudo<(outs GPR64:$Rt), (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), []>;
def FakeStore64 : Pseudo<(outs), (ins GPR64:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), []>;
}
def AArch64fakeload64 : SDNode<"AArch64ISD::FakeLoad64", SDTIntBinOp, [SDNPHasChain]>;
def AArch64fakestore64 : SDNo...
2018 Dec 05
2
Strange regalloc behaviour: one more available register causes much worse allocation
...%399:gpr64
7764B %402:gpr32 = COPY %404:gpr32
7768B %407:gpr32 = COPY %409:gpr32
7776B %412:gpr32 = COPY %414:gpr32
7780B %417:gpr32 = COPY %419:gpr32
7788B %422:gpr32 = COPY %424:gpr32
7792B %427:gpr32 = COPY %429:gpr32
7800B %432:gpr64 = COPY %434:gpr64
7808B %373:gpr64sp = IMPLICIT_DEF
7816B %374:gpr64sp = IMPLICIT_DEF
8048B B %bb.30
Looking at the debug output of the register allocator, the sequence of events
which kicks things off is
%223 assigned to w0
%283 evicts %381 from w15
%381 requeued for second round
%253 assigned to w15
%381 split for w15...
2018 Dec 05
3
Strange regalloc behaviour: one more available register causes much worse allocation
...%399:gpr64
7764B %402:gpr32 = COPY %404:gpr32
7768B %407:gpr32 = COPY %409:gpr32
7776B %412:gpr32 = COPY %414:gpr32
7780B %417:gpr32 = COPY %419:gpr32
7788B %422:gpr32 = COPY %424:gpr32
7792B %427:gpr32 = COPY %429:gpr32
7800B %432:gpr64 = COPY %434:gpr64
7808B %373:gpr64sp = IMPLICIT_DEF
7816B %374:gpr64sp = IMPLICIT_DEF
8048B B %bb.30
Looking at the debug output of the register allocator, the sequence of events
which kicks things off is
%223 assigned to w0
%283 evicts %381 from w15
%381 requeued for second round
%253 assigned to w15
%381 split for w15...