search for: sdtintbinop

...this result for a simple case is bothersome. >> > > Are you marking add as commutable? Are you making mov as a copy > instruction? > How do I mark them? For the commutative property, I observed this definition: def add : SDNode<"ISD::ADD" , SDTIntBinOp , [SDNPCommutative, SDNPAssociative]>; ... and assumed it was sufficient, since I saw no other targets making special arrangements. I see no obvious (to me, anyway 8^) "copy instruction" property. The insn in question is generated by copyRegToReg(), and s...

...{ def FakeLoad64 : Pseudo<(outs GPR64:$Rt), (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), []>; def FakeStore64 : Pseudo<(outs), (ins GPR64:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend), []>; } def AArch64fakeload64 : SDNode<"AArch64ISD::FakeLoad64", SDTIntBinOp, [SDNPHasChain]>; def AArch64fakestore64 : SDNode<"AArch64ISD::FakeStore64", SDTIntBinOp, [SDNPHasChain]>; to AArch64ISD in AArch64ISelLowering.h below ISD::FIRST_TARGET_MEMORY_OPCODE: FakeLoad64, FakeStore64 in AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(): Smal...

...2) > diff --git a/lib/Target/R600/AMDGPUInstrInfo.td b/lib/Target/R600/AMDGPUInstrInfo.td > index 3d70791..1600c4a 100644 > --- a/lib/Target/R600/AMDGPUInstrInfo.td > +++ b/lib/Target/R600/AMDGPUInstrInfo.td > @@ -91,6 +91,12 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp, > [SDNPCommutative, SDNPAssociative] > >; > > +// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0 > +def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>; > + > +// out = (src1 > src0) ? 1 : 0 > +def AMDGPUborrow : SDNode<"AMDGPUISD:...

On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > I have my new port limping enough to compile a very basic function: > > int > foo (int a, int b, int c, int d) > { > return a + b - c + d; > } > > clang-cc -O2 yields: > > define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { > entry: > %add = add i32 %b, %a ; <i32> [#uses=1]

...s bothersome. >>> >> >> Are you marking add as commutable? Are you making mov as a copy >> instruction? >> > > How do I mark them? For the commutative property, I observed this > definition: > > def add : SDNode<"ISD::ADD" , SDTIntBinOp , > [SDNPCommutative, SDNPAssociative]>; Yes, the "target-independent" ISD::ADD node is commutative. But it doesn't mean the target specific instruction it is selected to has to be commutative. > > ... and assumed it was sufficient, since I s...

Hi, A piece of code in a target description file: def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; May I understand "SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>" as below? (Z = X + Y, for example); Z:0 X:1 Y:2 X ha...

Hello Per, > The CMPrr instruction is moved down to after the PHI node. My guess is that > the 'dead' in CFR<imp-def,dead> is to blame, but I can't see what I'm doing > differently from MSP430/sparc that makes this not work. Any help GREATLY > appreciated! It seems like no use of CFR after CMP, indeed. How condbranches on your platform look like (patterns, etc.)

Hi list, I'm trying to match a particular pattern into the SDag which looks like this: // non-commutative multiplication def ncmul : SDNode<"ISD::MUL" , SDTIntBinOp, [SDNPAssociative]>; def mula_pat : PatFrag<(ops node:$a, node:$b), (add (ncmul (sext (i16 (extractelt node:$a, (i32 0)))),...

...t's used on the next row: %reg16388<def> = CMPrr %reg16384, %reg16385, %CFR<imp-def,dead>; IntRegs:%reg16388,16384,16385 SKIPCOND 1, *%CFR<imp-use>* Or doesn't that count? Following are patters for cmp and skipcond: def cmpcc : SDNode<"CSISD::CMP", SDTIntBinOp, [SDNPOutFlag]>; let Defs = [CFR] in { def CMPrr : InstCS<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), "cmp $c, $dst", [(set IntRegs:$dst, (cmpcc IntRegs:$b, IntRegs:$c)), (implicit CFR)]>; } let Uses = [CFR], isBranch = 1, isTerminato...

I have my new port limping enough to compile a very basic function: int foo (int a, int b, int c, int d) { return a + b - c + d; } clang-cc -O2 yields: define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: %add = add i32 %b, %a ; <i32> [#uses=1] %sub = sub i32 %add, %c ; <i32> [#uses=1] %add4 = add i32 %sub, %d ; <i32>

Hello! I'm working on a new back-end and have hit a bit of a snag. I'm working on getting selectcc working and have followed the MSP430 model of emitting a custom CMP and SELECT_CC node and matching that with a pseudo-instruction that has useCustomEmitter=1. However, my output ends up very wrong, despite the Machine code being initially correct: # Machine code for function func: Function

...; > + > +// out = max(a, b) a and b are floats > +def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp, > + [SDNPCommutative, SDNPAssociative] > +>; > + > +// out = max(a, b) a and b are signed ints > +def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp, > + [SDNPCommutative, SDNPAssociative] > +>; > + > +// out = max(a, b) a and b are unsigned ints > +def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp, > + [SDNPCommutative, SDNPAssociative] > +>; > + > +// out = min(a, b) a and b are floats >...