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...inter is pointing to useful data. Could anyone working on x86 instruction selection give some pointers to prevent this? Thanks, -Peng ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1 %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2 MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112 %vre...

...tes R0-R3 are used as inputs to a function. R1-R4 are marked as calleesaved. From the above code I cannot see any reason why R1 & R2 are being spilled, I assume the fault lies in my tablegen definitions (relevant ones reproduced below) : let isCommutable=1 in { def ADD32rrr : M819Inst<(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),"ADD.L\t{$dst,$src1 + $src2}",[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; } def ADD32rri : M819Inst<(outs GR32:$dst),(ins GR32:$src1, i32imm:$src2),"ADD.L\t{$dst,$src1 + $src2}",[(set GR32:$dst, (add GR32:$src1, imm:$src2))]>; d...

..._max_qb, "iii", "") I define the intrinsic as Pseudo instruction,it succeed. But when mapping a new instruction.I don't know how to do. In x86InstrArithmetic.td. I add ,(To make sure the Sched is right, I use the WriteIMul16Reg ) def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32 ; when compile LLVM , the error appears. "[ 97%] Updating X86GenAsmWriter1.inc... Unhandled immediate encoding GR32 U...

...ould anyone working on x86 instruction selection give some pointers to prevent this? > > Thanks, > -Peng > > > ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>, %ESP<imp-use> ; line 1 > %vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2 > MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3 > %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %nore...

...vm/trunk/lib/Target/X86/X86InstrSSE.td Thu May 26 18:13:19 2011 > @@ -4935,66 +4935,66 @@ > // This set of instructions are only rm, the only difference is the size > // of r and m. > let Constraints = "$src1 = $dst" in { > - def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst), > + def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst), > (ins GR32:$src1, i8mem:$src2), > "crc32{b} \t{$src2, $src1|$src1, $src2}", > [(set GR32:$dst, > - (int_x86...

...@llvm.dbg.value(metadata i32 %5, metadata !28, metadata !DIExpression()), !dbg !50 > ret i32 %6, !dbg !52 > ____________________________________________________ > After phi-elimination, it is > > bb.3.vaarg.end: > ; predecessors: %bb.2, %bb.1 > > %5:gr32 = COPY killed %18:gr32, debug-location !50; phi.ll:21:1 // %18 was def in all predecessors //phi --> COPY killed %18 > %17:gr32 = ADD32rr killed %8:gr32(tied-def 0), killed %5:gr32, implicit-def dead $eflags, debug-location !41; phi.ll:12:1...

...the schedule of an instruction tells the machine how to do . I don't konw if it's right. For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication. def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32; And in X86ScheduleXXX.td ,there is definition of Ports and so on. My questions are here,as followi...

...return "X86ISD::max_qb"; In /lib/Target/X86/X86InstrInfo.td: def X86max_qb_flag : SDNode<"X86ISD::max_qb", SDTBinaryArithWithFlags, [SDNPCommutative]>; In /lib/Target/X86/X86InstrArithmetic.td: def max_qb : I<0xff,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2|$src1,$src2, $dst}", [(set GR32:$dst,EFLAGS,(X86max_qb_flag GR32:$src1, GR32:$src2))]>, Sched<[WriteIMul]>, TB, OpSize32 ; I think it can be work ,at least work as one multiplication(beca...

...the schedule of an instruction tells the machine how to do . I don't konw if it's right. For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication. def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32; And in X86ScheduleXXX.td ,there is definition of Ports and so on. My questions are here,as followi...

...ne code for function test3: Frame Objects: fi#-2: size=4, align=4, fixed, at location [SP+8] fi#-1: size=4, align=8, fixed, at location [SP+4] Function Live Outs: %EAX BB#0: derived from LLVM BB %entry %reg16385<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-2] GR32:%reg16385 %reg16384<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-1] GR32:%reg16384 %reg16388<def> = MOV32ri 1; GR32:%reg16388 %reg16392<def> = XOR32ri %reg16385, 4294967294, %EFLAGS<imp-def>; GR32:%reg16392,16385 %reg16391&...

My architecture has an FPU, but uses integer registers to store floating-point values. So each register can store either an int or an IEEE float. I define a register class like this: def GR32 : RegisterClass<"MyArch", [i32, f32], 32, (sequence "R%u", 0, 32)>; So far so good. However, when I write a rule to store a register: def STORE32r : S32< (outs), (ins GR32:$rS, GR32:$rD), "st {$rS, ($rD)}", [(store GR32:$rS, (iPTR GR32:$rD))]>; ...th...

...e for function test5: Frame Objects: fi#-2: size=2, align=4, fixed, at location [SP+8] fi#-1: size=2, align=8, fixed, at location [SP+4] Function Live Outs: %AX BB#0: derived from LLVM BB %entry %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%...

Currently, instruction selection patterns are defined like this: def : Pat<(and (not GR32:$src1), GR32:$src2), (ANDN32rr GR32:$src1, GR32:$src2)>; def : Pat<(and (not GR64:$src1), GR64:$src2), (ANDN64rr GR64:$src1, GR64:$src2)>; TableGen infers the types of $src1 and $src2 from the specified register classes, and that is the only purpose of the regis...

...nserter (it's basically a main function with a printf and a return inside it): # Machine code for function main: SSA BB#0: derived from LLVM BB %entry ADJCALLSTACKDOWN64 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg2<def> = MOV32ri64 <ga:@str>; GR32:%vreg2 %vreg3<def> = SUBREG_TO_REG 0, %vreg2<kill>, 4; GR64:%vreg3 GR32:%vreg2 %RDI<def> = COPY %vreg3; GR64:%vreg3 CALL64pcrel32 <ga:@puts>, <regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<im...

On Sep 1, 2010, at 11:14 AM, Dale Johannesen wrote: > > On Sep 1, 2010, at 6:25 AMPDT, Argyrios Kyrtzidis wrote: > >> The attached .ll files seem equivalent, but the resulting asm from >> 'opt-fail.ll' causes a crash to webkit. >> I suspect the usage of registers is wrong, can someone take a look ? > > Yes, the code here is wrong: > >> movl

..., c; a=1;b=2; c = int_x86_max_qb(a, b); } When I use clang to compile，there is a warning:implicit declaration of function 'int_x86_max_qb' is invalid in C99 [-Wimplicit-function-declaration]. So I add the definition in src/lib/Target/X86/X86InstrInfo.td def MAX_QB : I<0xff,RawFrm, (outs GR32:$Rd), (ins GR32:$src1,GR32:$src2),"max_qb \t $Rd $src1 $src2", []>, OpSize32; But it doesn't work.What should I do to make it correct? please tell me.Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-...

...g register allocation, or how can I tell from (1) that I cannot execute %reg16385<def> = COPY %reg16390. Furthermore, how should I handle this case. > BB#0: derived from LLVM BB %entry > %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 > %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 > %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 > %reg16384<def> = COPY %reg16391:sub_16bit<k...

....edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu, llvmdev at cs.uiuc.edu > Sent: Thursday, March 21, 2013 1:26:25 PM > Subject: [LLVMdev] Simpler types in TableGen isel patterns > > Currently, instruction selection patterns are defined like this: > > def : Pat<(and (not GR32:$src1), GR32:$src2), > (ANDN32rr GR32:$src1, GR32:$src2)>; > def : Pat<(and (not GR64:$src1), GR64:$src2), > (ANDN64rr GR64:$src1, GR64:$src2)>; > > TableGen infers the types of $src1 and $src2 from the specified > register classes, and that is...

...love to hear about it. > > If you wonder about the liveness information, you can perform experiments like this (I'm using a NOOP instruction with an implicit use operand to produce some artificial uses). > > $ cat test.mir > name: somefunc > body: | > bb.0: > %0:gr32 = MOV32ri 42 > JB_1 %bb.2, undef implicit $eflags > JMP_1 %bb.2 > > bb.1: > %1:gr32 = MOV32ri 17 > JMP_1 %bb.3 > > bb.2: > NOOP implicit %0 > %1 = COPY %0 > JMP_1 %bb.3 > > bb.3: > NOOP implicit %1 > > >...

...N/ADJCALLSTACKUP slightly. Doing the mov->push transformation before PEI means I'd have to leave the ADJCALLSTACKDOWN/UP pair unbalanced. E.g. something like: ADJCALLSTACKDOWN32 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> %vreg9<def,dead> = COPY %ESP; GR32:%vreg9 PUSH32rmm %vreg0, 1, %noreg, 28, %noreg, %ESP<imp-def>, %ESP<imp-use>; GR32:%vreg0 PUSH32rmm %vreg0, 1, %noreg, 24, %noreg, %ESP<imp-def>, %ESP<imp-use>; GR32:%vreg0 PUSH32rmm %vreg0, 1, %noreg, 20, %noreg, %ESP<imp-def>, %ESP<imp-use>; GR32:%vreg0 PUS...