Displaying 3 results from an estimated 3 matches for "multipattern".
2008 Sep 23
0
[LLVMdev] Store patterns accepting i32 only?
...uot;,
> [(global_store GPR:$val, ADDR:$ptr)]>;
>
> I want this same pattern to be able to accept all the types for val
> that GPR is mapped to(i32, i64, f32, f64).
> Is there any way I can modify this so that it do what I want?
You probably want to use a multipattern ("defm"). This allows a
single "line" of TD file to expand into multiple 'def's. Take a look
at the X86 SSE instructions for some examples of this. Also, the
tblgen document has some info as well,
-Chris
>
> Here is a snippet of the generated code with t...
2008 Sep 23
2
[LLVMdev] Store patterns accepting i32 only?
I'm trying to write a store pattern that accepts both i32 and f32,
however, when tablegen generates the code, it only generates the code
for i32 only.
def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
def MEM : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops GPR, GPR);
}
def global_st :
2014 Mar 19
2
[LLVMdev] Type inference on registers with can contain multiple types
...>;
...then I get the dreaded 'cannot infer all types in pattern' error.
This is presumably because tablegen can't tell whether the input is an
i32 or a f32.
What's the best thing to do here? Explicitly annotating the input type
works, of course, but then I need two rules. Use a multipattern? Or is
there a way to tell tablegen that the input is allowed to be either?
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