After PrologEpilogCodeInserter I found that the instructions that restore callee
saved registers S0,S1,LR are in the wrong location ,the instructions are:
%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]
%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]
%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]
(LR is the Return address register)
the whole code of print-machineinstrs are:
# After PrologEpilogCodeInserter:
# Machine code for function L_mpy_ls: Post SSA
BB#0: derived from LLVM BB %0
Live Ins: %LR %S1 %S0
%SP<def> = ADDI %SP, -48
PROLOG_LABEL <MCSym=_tmp0>
ST %LR<kill>, %SP, 44; mem:ST4[FixedStack0]
ST %S1<kill>, %SP, 40; mem:ST4[FixedStack1]
ST %S0<kill>, %SP, 36; mem:ST4[FixedStack2]
PROLOG_LABEL <MCSym=_tmp1>
%S0<def> = LD %SP, 48; mem:LD4[FixedStack-1](align=8)
ST %S0, %SP, 0; mem:ST4[FixedStack-4](align=8)
JSUB <ga:@extract_l>, <regmask>, %LR<imp-def>,
%SP<imp-def>, %V0<imp-def>
%V1<def> = ADDI %ZERO, 1
ST %V0<kill>, %SP, 0; mem:ST4[FixedStack-5](align=8)
ST %V1<kill>, %SP, 4; mem:ST4[FixedStack-6]
JSUB <ga:@shr>, <regmask>, %LR<imp-def>, %SP<imp-def>,
%V0<imp-def>
%S1<def> = LD %SP, 52; mem:LD4[FixedStack-2]
%V1<def> = LIL 32767
%V0<def> = AND %V0<kill>, %V1<kill>
ST %V0<kill>, %SP, 4; mem:ST4[FixedStack-8]
ST %S1, %SP, 0; mem:ST4[FixedStack-7](align=8)
JSUB <ga:@L_mult>, <regmask>, %LR<imp-def>,
%SP<imp-def>, %V0<imp-def>
%V1<def> = ADDI %ZERO, 15
ST %V0<kill>, %SP, 0; mem:ST4[FixedStack-9](align=8)
ST %V1<kill>, %SP, 4; mem:ST4[FixedStack-10]
JSUB <ga:@L_shr>, <regmask>, %LR<imp-def>, %SP<imp-def>,
%V0<imp-def>
ST %S0<kill>, %SP, 0; mem:ST4[FixedStack-11](align=8)
%S0<def> = COPY %V0
JSUB <ga:@extract_h>, <regmask>, %LR<imp-def>,
%SP<imp-def>, %V0<imp-def>
ST %S0<kill>, %SP, 0; mem:ST4[FixedStack-12](align=8)
ST %S1<kill>, %SP, 4; mem:ST4[FixedStack-13]
ST %V0<kill>, %SP, 8; mem:ST4[FixedStack-14](align=8)
%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]
%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]
%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]
JSUB <ga:@L_mac>, <regmask>, %LR<imp-def>, %SP<imp-def>,
%V0<imp-def>
%SP<def> = ADDI %SP, 48
RetLR %V0<imp-use>
what I want to get is :
......
JSUB <ga:@extract_h>, <regmask>, %LR<imp-def>,
%SP<imp-def>, %V0<imp-def>
ST %S0<kill>, %SP, 0; mem:ST4[FixedStack-12](align=8)
ST %S1<kill>, %SP, 4; mem:ST4[FixedStack-13]
ST %V0<kill>, %SP, 8; mem:ST4[FixedStack-14](align=8)
JSUB <ga:@L_mac>, <regmask>, %LR<imp-def>, %SP<imp-def>,
%V0<imp-def>
%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]
%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]
%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]
%SP<def> = ADDI %SP, 48
RetLR %V0<imp-use>
can you tell me the problem? Thank you!
Best Regards,
Jiangwei Xu
Shanghai Jiao Tong University
800 Dongchuan Road
Shanghai, 200240
P.R.China
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