Displaying 6 results from an estimated 6 matches for "fixedstack1".
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2017 Oct 13
2
[SelectionDAG] Assertion due to MachineMemOperand flags difference.
...haven't considered.
I have a patch posted implementing 2, but don't know if I should look
at fixing 1 as well (or perhaps instead). The loads that trigger the
assertion are:
t47: v4i32,ch = load<LD16[%0+80](align=8)(dereferenceable)> t20, t46, undef:i64
t69: v4i32,ch = load<LD16[FixedStack1+80](align=8)> t50, t46, undef:i64
I would expect the the second load should also be marked
dereferenceable since its loading from one of the TargetFrames. Am I
on the right track here?
Thanks
Sean
-------------- next part --------------
Initial selection DAG: BB#0 '_Z3fn2v:entry'
Selec...
2013 Nov 22
0
[LLVMdev] PrologEpilogProblems;
After PrologEpilogCodeInserter I found that the instructions that restore callee saved registers S0,S1,LR are in the wrong location ,the instructions are:
%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]
%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]
%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]
(LR is the Return address register)
the whole code of print-machineinstrs are:
# After PrologEpilogCodeInserter:
# Machine code for function L_mpy_ls: Post SSA
BB#0: derived from LLVM BB %0
Live Ins: %LR %S1 %S0
%SP<def> = ADDI %SP, -48
P...
2017 Sep 21
1
VSelect Instruction Error
Hello,
I am getting this error. What instruction is required to be implemented?
LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16
t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>,
undef:i64
t659: i64 = FrameIndex<1>
t10: i64 = undef
t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0,
t8, undef:i64
t8: i64 = add t7, Constant:i64<4>
t7: i64 = add t2, t63
t2: i64,ch = Co...
2017 Oct 25
3
How vregs are assigned to operands in IR
...}
Generated machine instructions (initial)
BB#0: derived from LLVM BB %entry
%vreg11<def> = MOVi32imm 6; GPR32:%vreg11
%vreg12<def> = MOVi32imm 5; GPR32:%vreg12
STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
STRWui %vreg12, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg12
STRWui %vreg11, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg11
.................................
Best
Nisal
2013 Dec 21
0
[LLVMdev] Order of glued nodes during scheduling
...EXTRACT_SUBREG 0x10015677970, 0x10015679080, 0x10015678d80:1 [ORD=49] [ID=2]
0x10015678d80: i32,glue = ANDIo 0x100156746c0, 0x10015671b80 [ORD=49] [ID=2]
and scheduled together, yielding this schedule:
SU(3): 0x100156746c0: i32,ch = LWZ 0x10015674fc0, 0x10015678b80, 0x10015672280<Mem:LD4[FixedStack1+8](align=8)> [ORD=49] [ID=3]
SU(2): 0x100156749c0: i1 = EXTRACT_SUBREG 0x10015677970, 0x10015679080, 0x10015678d80:1 [ORD=49] [ID=2]
0x10015678d80: i32,glue = ANDIo 0x100156746c0, 0x10015671b80 [ORD=49] [ID=2]
SU(1): 0x10015671d80: ch = CopyToReg 0x100156463c8, 0x10015677c70, 0x100156749c...
2013 Oct 22
1
[LLVMdev] System call miscompilation using the fast register allocator
...%RDI<kill>
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RDI<imp-def>
%RAX<def> = MOV64ri64i32 54
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RSI<imp-def>
MOV64mr %RSP, 1, %noreg, -16, %noreg, %RDX<kill>; mem:ST8[FixedStack1]
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %RDX<imp-def>
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %R10<imp-def>
INLINEASM <es:> [sideeffect] [attdialect], $0:[regdef], %R8<imp-def>
INLINEASM <es:syscall
>...