Displaying 20 results from an estimated 58 matches for "fixedstack".
2013 Nov 22
0
[LLVMdev] PrologEpilogProblems;
After PrologEpilogCodeInserter I found that the instructions that restore callee saved registers S0,S1,LR are in the wrong location ,the instructions are:
%S0<def> = LD %SP, 36; mem:LD4[FixedStack2]
%S1<def> = LD %SP, 40; mem:LD4[FixedStack1]
%LR<def> = LD %SP, 44; mem:LD4[FixedStack0]
(LR is the Return address register)
the whole code of print-machineinstrs are:
# After PrologEpilogCodeInserter:
# Machine code for function L_mpy_ls: Post SSA
BB#0: derived from LLVM BB %0
Liv...
2010 Nov 08
2
[LLVMdev] [LLVMDev] Register Allocation and copy instructions
...# Machine code for function test5:
Frame Objects:
fi#-2: size=2, align=4, fixed, at location [SP+8]
fi#-1: size=2, align=8, fixed, at location [SP+4]
Function Live Outs: %AX
BB#0: derived from LLVM BB %entry
%reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0;
mem:LD2[FixedStack-2] GR32:%reg16390
%reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385
GR32:%reg16390
%reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0;
mem:LD2[FixedStack-1] GR32:%reg16391
%reg16384<def> = COPY %reg16391:sub_16bit<kill>...
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
...gt;dump()
# Machine code for function PointToHPoint:
Frame Objects:
fi#-1: size=48, align=8, fixed, at location [SP+8]
fi#0: size=32, align=8, at location [SP]
Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2
BB#0: derived from LLVM BB %entry
SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2
SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1
%vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0
%vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4
The first two stores write the values in argument registers $6 and $7
to f...
2016 Jul 30
1
Instruction selection bug for vector store with FixedStack
Hello.
Could you please help me solve the following LLC bug happening at instruction
selection time:
ISEL: Starting pattern match on root node: t172: ch = store<ST64[FixedStack6]>
t0, t6, FrameIndex:i64<6>, undef:i64
Initial Opcode index to 157
Skipped scope entry (due to false predicate) at index 162, continuing at 236
Match failed at index 241
Continuing at 263
LLVM ERROR: Cannot select: t172: ch = store<...
2010 Oct 29
1
[LLVMdev] [LLVMDev] Register Allocation and Kill Flags
...r.ll
# Machine code for function test3:
Frame Objects:
fi#-2: size=4, align=4, fixed, at location [SP+8]
fi#-1: size=4, align=8, fixed, at location [SP+4]
Function Live Outs: %EAX
BB#0: derived from LLVM BB %entry
%reg16385<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0;
mem:LD4[FixedStack-2] GR32:%reg16385
%reg16384<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0;
mem:LD4[FixedStack-1] GR32:%reg16384
%reg16388<def> = MOV32ri 1; GR32:%reg16388
%reg16392<def> = XOR32ri %reg16385, 4294967294, %EFLAGS<imp-def>;
GR32:%reg16392,16385
%r...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<<<<<<<<<&...
2012 Mar 07
0
[LLVMdev] Question about post RA scheduler
...tion PointToHPoint:
> Frame Objects:
> fi#-1: size=48, align=8, fixed, at location [SP+8]
> fi#0: size=32, align=8, at location [SP]
> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2
>
> BB#0: derived from LLVM BB %entry
> SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2
> SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1
> %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0
> %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4
>
>
> The first two stores write the values in arg...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...; I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<...
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
...me Objects:
>> fi#-1: size=48, align=8, fixed, at location [SP+8]
>> fi#0: size=32, align=8, at location [SP]
>> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2
>>
>> BB#0: derived from LLVM BB %entry
>> SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2
>> SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1
>> %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0
>> %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4
>>
>>
>> The fir...
2012 Sep 20
2
[LLVMdev] Scheduling question (memory dependency)
..., fixed, at location [SP+50]
Function Live Ins: %X3 in %vreg1, %X4 in %vreg2
0B BB#0: derived from LLVM BB %entry
Live Ins: %X3 %X4
16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
32B %vreg1<def> = COPY %X3; G8RC:%vreg1
48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1] G8RC:%vreg1
64B %vreg4<def> = LHA 0, <fi#-1>; mem:LD2[%0] GPRC:%vreg4
...
---------------------------------------------------------------
So far, so good. When we get to list scheduling, not quite so good:
----------------------------------------------------------...
2010 Sep 29
2
[LLVMdev] comparison pattern trouble
...ing the following bug:
Code
%0 = zext i8 %data to i32
%1 = zext i16 %crc to i32
%2 = xor i32 %1, %0
%3 = and i32 %2, 1
%4 = icmp eq i32 %3, 0
which compares the lowest bits of the 2 variables
ends up being compiled as
%reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384
%reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385
%reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384
%reg16390<def> = NErrb %reg16384, %reg16385; I1Regs:%reg16390 I32Regs:%reg16384,16385
which just...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...whether this helps or not. Later the lowered instructions
look like:
------------------------------------------------------------------
16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
32B %vreg1<def> = COPY %X3; G8RC:%vreg1
48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1] G8RC:%vreg1
64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
...
------------------------------------------------------------------
Note the %i11 instead of %0 on the LHZ as another difference. The
scheduler then generates a dependency between the store...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...= [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %vreg30<def> = LDriw <fi#-1>, 0;
mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
IntRegs:%vreg31
24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
28B %vreg106<def> = TFRI 16777216;
IntRegs:%vreg106<<<<<<<...
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
...> %1 = zext i16 %crc to i32
> %2 = xor i32 %1, %0
> %3 = and i32 %2, 1
> %4 = icmp eq i32 %3, 0
>
>
> which compares the lowest bits of the 2 variables
>
>
> ends up being compiled as
>
>
> %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384
> %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385
> %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384
> %reg16390<def> = NErrb %reg16384, %reg16385; I1Regs:%reg16390 I32Regs:%reg16384,16385
&...
2012 Mar 13
0
[LLVMdev] Question about post RA scheduler
...fi#-1: size=48, align=8, fixed, at location [SP+8]
>>> fi#0: size=32, align=8, at location [SP]
>>> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2
>>>
>>> BB#0: derived from LLVM BB %entry
>>> SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2
>>> SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1
>>> %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0
>>> %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4
>>>
>>...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...ter the lowered instructions
> look like:
>
> ------------------------------------------------------------------
> 16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
> 32B %vreg1<def> = COPY %X3; G8RC:%vreg1
> 48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1]
> G8RC:%vreg1
> 64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
> ...
> ------------------------------------------------------------------
>
> Note the %i11 instead of %0 on the LHZ as another difference. The
> scheduler then genera...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote:
> The code in collectRanges() does:
>
> // Collect ranges for register units. These live ranges are computed on
> // demand, so just skip any that haven't been computed yet.
> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
> for (MCRegUnitIterator Units(Reg,
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
> 12B %vreg30<def> = LDriw <fi#-1>, 0;
> mem:LD4[FixedStack-1](align=8) IntRegs:%vreg30
> 20B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2]
> IntRegs:%vreg31
> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26
> 28B %vreg106<def> = TFRI 16777216;
> IntRegs:%vreg106<<<<<<<<<...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...> >
> > > ------------------------------------------------------------------
> > > 16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
> > > 32B %vreg1<def> = COPY %X3; G8RC:%vreg1
> > > 48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1]
> > > G8RC:%vreg1
> > > 64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
> > > ...
> > > ------------------------------------------------------------------
> > >
> > > Note the %i11 instead of %0 on th...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
The code in collectRanges() does:
// Collect ranges for register units. These live ranges are computed on
// demand, so just skip any that haven't been computed yet.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))