llvm dev - Sep 2013 - [LLVMdev] Disassembler Issue

I'm having trouble getting TableGen to generate disassembler code.
The issue is that I have several TableGen definitions that emit the
same instruction encoding.  This results in TableGen complaining about
encoding conflicts (and not handling those instructions).

For example, general purpose registers in the architecture I'm
targeting can hold floating point or integer values.  As such, I
created a multiclass for load/store instructions that have both
integer and floating point patterns. I've done similar things in other
areas, for example, ctlz and ctlz_zero_undef.

All of this stuff works fine for everything except when trying to
create a disassembler. My question is what the proper way is to make
several instruction patterns map to the same instruction encoding,
something that doesn't confuse the disassembler.

Thanks

--Jeff

Hi Jeff,
> All of this stuff works fine for everything except when trying to
> create a disassembler. My question is what the proper way is to make
> several instruction patterns map to the same instruction encoding,
> something that doesn't confuse the disassembler.
This is usually handled by InstAlias instances for any different
assembly syntax and Pat instances to add extra types for CodeGen.

Cheers.

Tim.