search for: ctlz_zero_undef

Hi Eli, Thanks for pointing to the CTLZ_ZERO_UNDEF “LibCall” implementation. I have not it in the version that I am currently using, so it’s nice to know that it’s implemented now. Incidentally, the CTLZ… implementation is IDENTICAL to what I am proposing for the Shifts. This is not just adding support for “out-of-tree-targets”, but giving consis...

LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def. The library functions defined in RuntimeLibCalls.def (among others) are these: HANDLE_LIBCALL(SRA_I16, "__ashrhi3") HANDLE_LIBCALL(SRA_I32, "__ashrsi3") HANDLE_LIBCALL(SRA_I64, "__ashrdi3") However, setting

...t; Sent: Monday, June 10, 2019 3:05 PM > To: Eli Friedman <efriedma at quicinc.com> > Cc: llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] Re: [llvm-dev] Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL > > Hi Eli, > > Thanks for pointing to the CTLZ_ZERO_UNDEF “LibCall” implementation. I have not it in the version that I am currently using, so it’s nice to know that it’s implemented now. > > Incidentally, the CTLZ… implementation is IDENTICAL to what I am proposing for the Shifts. This is not just adding support for “out-of-tree-targets”, but gi...

...For example, general purpose registers in the architecture I'm targeting can hold floating point or integer values. As such, I created a multiclass for load/store instructions that have both integer and floating point patterns. I've done similar things in other areas, for example, ctlz and ctlz_zero_undef. All of this stuff works fine for everything except when trying to create a disassembler. My question is what the proper way is to make several instruction patterns map to the same instruction encoding, something that doesn't confuse the disassembler. Thanks --Jeff

...ot;BCNT_INT", ctpop, VecALU>; > > +def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; > +def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; > + > def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", ctlz_zero_undef, VecALU>; > def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; > > diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp > index 9b2b689..a28b76a 100644 > --- a/lib/Target/R600/R600ISelLowering.cpp >...