llvm dev - Jan 2013 - [LLVMdev] Generating unusual instruction

I have seen that most of the targets do comparison and branching
in two separate instructions e.g. 'cmpl' followed by 'br' in x86
or the
like.
LLVM IR is also in same manner.

I want to implement comparison+branching in one instruction like

       beq r1, r2, .label   #if r1==r2 then jump to .label

How to merge two instruction into one.

Regards
Vikram Singh



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Hi,

Have you try to directly describe such patterns in tblgen file? Like this:
(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)

MIPS backend does that. I also do this in my own backend, and seem to be
working fine.


On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com>
wrote:
> I have seen that most of the targets do comparison and branching
> in two separate instructions e.g. 'cmpl' followed by 'br'
in x86 or the
> like.
> LLVM IR is also in same manner.
>
> I want to implement comparison+branching in one instruction like
>
>        beq r1, r2, .label   #if r1==r2 then jump to .label
>
> How to merge two instruction into one.
>
> Regards
> Vikram Singh
>
>
>
> --
> View this message in context:
>
http://llvm.1065342.n5.nabble.com/Generating-unusual-instruction-tp53192.html
> Sent from the LLVM - Dev mailing list archive at Nabble.com.
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>


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Regards,
Dongrui
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Thanks, I tried to go thru the Mips code to see the code related to the
branch implementation. But there are many fragments in the MipsInstrInfo.td
and also many Pat statements. Please help me in regard of these points.
1. I find it, as it seems to me, hard to refer Mips because I already have
taken Sparc code. Is there any way to modify Sparc code for eliminate SUBCC.
2. I find less literature on the .td file. for example consider
     [brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset, IIBranch]
    What is IIBranch.
3. What are these ZextLoad and the likes?

Regards
Vikram



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Hi Dongrui

I looked for MIPS tblgen .td file but in case MIPS also it is (1) first 
subtracting the two operand and then (2) comparing  the result with
zero. i.e. it is generating two insns. But i want that in just one.

Any help.....

Regard 
VSP



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