similar to: [LLVMdev] Generating unusual instruction

Hi, Have you try to directly describe such patterns in tblgen file? Like this: (brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset) MIPS backend does that. I also do this in my own backend, and seem to be working fine. On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com> wrote: > I have seen that most of the targets do comparison and branching > in two separate

Hi all, I am working on an out-of-tree target. I am wondering if it is possible to force the register allocator (and/or spiller) to not break certain instruction sequence. For example: phys_reg = MI1 vreg1 vreg 2 = MI2 phys_reg Is there a way to tell RA/spiller not to insert COPY or spill between MI1 and MI2? I am using greedy register allocator and inline spiller. -- Regards, Dongrui

Hi all, I understand from the document that I should be able to configure llvm with only specific targets by passing -DLLVM_TARGETS_TO_BUILD=some-backend to cmake. However, I get the following errors whenever I don't include X86 in the target list: CMake Error at cmake/modules/LLVMConfig.cmake:127 (message): Library `X86' not found in list of llvm libraries. Call Stack (most recent

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

Hi all, I'm developing a backend for a custom architecture. The target architecture has different memory for different data types(vector and scalar). So is it possible to maintain two different stacks, one for vector and the other for scalar? ---- Regards, Dongrui She -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Tue, Mar 15, 2011 at 6:34 PM, Dongrui She <sarevokcc at gmail.com> wrote: > However, I get the following errors whenever I don't include X86 in the > target list: on top of trunk, it seems cmake requires at least "native" (for yours, X86) target. (I reconfirmed with -DLLVM_TARGETS_TO_BUILD=ARM on x86) For workaround, you have to include "X86" always.

Hi all, I try to print the live-in and live-out registers for each basic block in a backend for my own target. And I can get a list of live-in registers directly in MachineBasicBlock. Is there a quick way to also get the list of live-out registers without redoing the analysis. I think this information is computed and stored somewhere. -- Regards, Dongrui -------------- next part

But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I

Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17

I am implementing a new backend and am pretty sure I don't quite understand "the way" one is supposed to implement conditional branches. My target CPU natively supports a conditional branch instruction that accepts a condition to test (equal, less than, etc.), two operands (two registers, or one register and one immediate), and finally a target PC to branch to if the comparison

Hi everyone, I have the following code (as part of a larger function): %0 = icmp eq i16 %a, 0 ; <i1> [#uses=1] br i1 %0, label %bb1, label %bb I would like to match this with a BRCOND, but all I get is an error message when compiling the above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19]

I have a back end which has both scalar and vector registers that alias each other. I'm having a problem generating the ISel from tablegen that appears only when a vector register class is declared to contain integer vectors. At that moment tablegen doesn't seem to be able to infer integer types in patterns that it was able to before, but I'm not clear on why that's the

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

On 12/21/2016 4:45 PM, Phil Tomson via llvm-dev wrote: > Here's our testcase: > > #include <stdio.h> > > struct flags { > unsigned frog: 1; > unsigned foo : 1; > unsigned bar : 1; > unsigned bat : 1; > unsigned baz : 1; > unsigned bam : 1; > }; > > int main() { > struct flags flags; > flags.bar = 1; >

Hi there, I'm having a hard time with promoting operands from i1 to i32 in my backend... I have to register classes, VTs are i1 and i32. The i1 registers are only for predication and conditional jumps, so I want to use them with brcond, setcc. There are no instructions to directly load a value in an i1 register or to copy between i1 and i32, so I need the DAG Legalizing Pass to not generate

> > > That's not it at all. These model instructions reading / writing > MVT::Flag a value. That just mean from the scheduler's point of view > the node that produces a MVT::Flag and the user have to be scheduled > together. Wow. That's just super confusing. So SDNPInFlag/SNDPOutFlag is used only for scheduling? I think you're misunderstanding ISD::SETCC.

Here's our testcase: #include <stdio.h> struct flags { unsigned frog: 1; unsigned foo : 1; unsigned bar : 1; unsigned bat : 1; unsigned baz : 1; unsigned bam : 1; }; int main() { struct flags flags; flags.bar = 1; flags.foo = 1; if (flags.foo == 1) { printf("Pass\n"); return 0; } else {

On Sun, 22 Apr 2007, Christopher Lamb wrote: > I have a back end which has both scalar and vector registers that > alias each other. I'm having a problem generating the ISel from > tablegen that appears only when a vector register class is declared > to contain integer vectors. At that moment tablegen doesn't seem to > be able to infer integer types in patterns that it was

Hi, >> DAGCombiner::visitBRCOND() has code: >> >> SDValue N1 = N->getOperand(1); >> SDValue N2 = N->getOperand(2); >> >> ... >> >> SDNode *Trunc = 0; >> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) { >> // Look past truncate. >> Trunc = N1.getNode(); >> N1 = N1.getOperand(0);

Hello, Im back trying to finish my backend to a simple RISC cpu SABRE now that most of the tedious process of examining undergraduate students is out of the way. I have managed to describe the registers and the instructions in the architecture and have added support for 32 bit immediates (thanks to Christopher Lamb) as the instruction set only supports 17 bit immediates directly. Could