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I am trying to build cross compiler for custom processor (say XYZ) but on compilation it is giving error llvm-build: error: invalid native target: XYZ (not in project) I have tried configuring like these 1. ./configure --target=XYZ 2. ./configure --target=XYZ --enable-targets=XYZ 3. ./configure --enable-targets=XYZ But every time it is not recognising the XYZ processor. What could be the

...earch the configure script for TARGETS_TO_BUILD, add your target to the lists there (some creativity required), and then reconfigure. Alternatively, you can change autotools/configure.ac and regenerate configure by running ./autoconf/AutoRegen.sh. On Wed, Sep 19, 2012 at 11:20 PM, Vikram Singh <vsp1729 at gmail.com> wrote: > I am trying to build cross compiler for custom processor (say XYZ) but > on compilation it is giving error > > llvm-build: error: invalid native target: XYZ (not in project) > > I have tried configuring like these > > 1. ./configure --target=XYZ &g...

Hi, Have you try to directly describe such patterns in tblgen file? Like this: (brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset) MIPS backend does that. I also do this in my own backend, and seem to be working fine. On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com> wrote: > I have seen that most of the targets do comparison and branching > in two separate instructions e.g. 'cmpl' followed by 'br' in x86 or the > like. > LLVM IR is also in same manner. > > I want to implement comparison+branching in one instr...

I have seen that most of the targets do comparison and branching in two separate instructions e.g. 'cmpl' followed by 'br' in x86 or the like. LLVM IR is also in same manner. I want to implement comparison+branching in one instruction like beq r1, r2, .label #if r1==r2 then jump to .label How to merge two instruction into one. Regards Vikram Singh -- View this

There is format in sparc <pre> subcc %r1, %r2, %r3 bne .label </pre> I want instruction like this <pre> bne %r1, %r2, .label </pre> </BR> I am referring to sparc code for this implementation (llvm-3.1).</BR></BR> 1. Should I change the SPBranch and BCOND structs in .td file.</BR> 2. Should I change BuildMI constructs in

I want to generate the instruction like addi 40, r3 ! i.e. r3 = r3 + 40 The format i wrote is def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))] but it is not compiling. what should be the format. vikram -- View this message

hi I am porting llvm 3.1 for a custom processor. I'm taking reference from sparc architecture. The problem I'm facing that sparc has 1 delay slot in call and conditional instructions. In my case some have 1 and some have 2 delay slots. But the backend is inserting only 1 delay slot instruction. I do not know how to insert more than 1 instruction in the delay slots. Please suggest some

Hi The construct in sparc def LEA_ADDri : F3_2<2, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr), "add ${addr:arith}, $dst", [(set IntRegs:$dst, ADDRri:$addr)]>; generate instruction like : add %fp, -20, %l1 in my port it generate like : addi %fp, -20, %r2 But the problem is that our ISA does not support the

Hi In sparc ABI the arguments are saved by the callee in the caller stack frame. Q. What to do to save them in callee stack frame itself. for example by default this is generated sti r2, -2(fp) sti r3, -3(fp) Instead how to generate sti r2, 4(fp) sti r3, 5(fp) The Indices are just for explanation. The matter is In sparc they are -ive which means in the caller

Hi folks How to place libcall for double precision number comparison. My machine does not have double precision comparison code but llvm is using single precision condition code deliberately. How to solve the problem. Regards VSP -- View this message in context: http://llvm.1065342.n5.nabble.com/Libcall-for-double-precision-comparison-tp59902.html Sent from the LLVM - Dev mailing list