llvm dev - Nov 2012 - [LLVMdev] TableGen: Requires in multiclass's def as well as defm

Hi,

I'd like to disallow ARM's register-register preload instruction for
NaCl
(and keep the register-immediate), and instead of my localmod being to
delete the 'rs' def from multiclass APreLoad I'd like to do the
cleaner
thing and have rs require IsNotNaCl. This unfortunately doesn't seem to
work because the subsequent defm have their own Requires.

The way preloads are set up right now makes sense and I don't think they
should be changed. Do I have the wrong approach in trying to add
Requires<[IsNotNaCl]> to multiclass APreLoad's def rs, and expecting
this
to be union'ed with defm PLD/PLDW/PLI's own Requires?

Thanks,

JF
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20121114/8b979815/attachment.html>