Hi Micah, On Tue, Jun 19, 2012 at 6:29 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:> If the patterns only include SDNodes, then pattern fragments will work. > > I might be wrong, but I've yet to find a way to do it with machine instructions, which is what you seem to have here.I found in the Cell SPU port: lib/Target/CellSPU/SPUMathInstr.td some examples using code fragments. I will try to see if that makes my code more readable. Thanks for your suggestions, Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
For reference, here is how the SPU port is using code and pattern fragments: // Holder of code fragments (you'd think this'd already be in // a td file somewhere... :-) class CodeFrag<dag frag> { dag Fragment = frag; } class I64SETCCNegCond<PatFrag cond, CodeFrag compare>: Pat<(cond R64C:$rA, R64C:$rB), (XORIr32 compare.Fragment, -1)>; def : I64SETCCNegCond<setne, I64EQr64>; def : I64SELECTNegCond<setne, I64EQr64>; Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
Interesting, I'll have to look into that. I have some pretty big pattern files I would love to refactor into simpler patterns. Micah> -----Original Message----- > From: Sebastian Pop [mailto:spop at codeaurora.org] > Sent: Wednesday, June 20, 2012 10:27 AM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] How to define macros in a tablegen file? > > For reference, here is how the SPU port is using code and pattern > fragments: > > // Holder of code fragments (you'd think this'd already be in > // a td file somewhere... :-) > > class CodeFrag<dag frag> { > dag Fragment = frag; > } > > class I64SETCCNegCond<PatFrag cond, CodeFrag compare>: > Pat<(cond R64C:$rA, R64C:$rB), > (XORIr32 compare.Fragment, -1)>; > > def : I64SETCCNegCond<setne, I64EQr64>; > def : I64SELECTNegCond<setne, I64EQr64>; > > > Sebastian > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote:> For reference, here is how the SPU port is using code and pattern fragments: > > // Holder of code fragments (you'd think this'd already be in > // a td file somewhere... :-)And this comment makes me think, shouldn't this class CodeFrag be included in the same place where PatFrag is declared: ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag ops, dag frag, code pred = [{}], such that we get it included through "llvm/Target/Target.td"? I will prepare a patch for this. Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
Apparently Analagous Threads
- [LLVMdev] How to define macros in a tablegen file?
- [LLVMdev] How to define macros in a tablegen file?
- [LLVMdev] How to define macros in a tablegen file?
- [LLVMdev] How to define macros in a tablegen file?
- [LLVMdev] [llvm-commits] How to define macros in a tablegen file?