search for: patfrag

...2. Entity followed after "(" is always need to be an operator? or it can be ValueType or something else? 3. What are keywords like "ins", "outs" and "ops"? They are not mentioned in lang ref manual either. 4. What is a "node" keyword? 5. How are PatFrags used? I see some .td files I see, like X86InstrFMA.td, PatFrag MemFrag is passed as argument to multiclass and then used along with addr:$src3 in it. I really don't understand what this means. Does this mean that whatever comes after PatFrag "object" is substituted as Args in PatFrag...

...match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops node:$val), (fneg node:$val), [{ return N->hasOneUse(); }]>; and then use that in each target instruction patten in XXXInstrInfo.td, such as: def XXX_MUL : XXXInst< (outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), "mul $dst, -$src1, $src2&q...

...gt; For reference, here is how the SPU port is using code and pattern fragments: > > // Holder of code fragments (you'd think this'd already be in > // a td file somewhere... :-) And this comment makes me think, shouldn't this class CodeFrag be included in the same place where PatFrag is declared: ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag ops, dag frag, code pred = [{}], such that we get it included through "llvm/Target/Target.td"? I will prepare a patch for this. Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Fo...

...32:$src1, GPR32:$src2))]>; def _fneg_rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), "!strcat(opc, " $dst, -$src1, $src2")", [(set $dst, (op (fneg_su GPR32:$src1), GPR32:$src2)))]>; } > I expect I can > define a PatFrag: > > def fneg_su : PatFrag<(ops node:$val), (fneg node:$val), [{ return > N->hasOneUse(); }]>; AFAIK, you don't need to verify for hasOneUse() because the instruction selector will do it for you. Also, it's too restrictive if fneg_su is used alone in some other matching...

Dear, I am looking at the Instructions defined in the XXXXInstrInfo.td where I can see a def record defined like below def ADD8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (*add *GR8:$src, GR8:$src2)), (implicit SRW)]>; Now here I would like the to

...def load_*" is almost identical. The only difference is the memory space name (global, constant, and etc.). I believe a for-loop can make it much more readable. (defining memory space patterns in PTXInstrInfo.td for each memory space) ---------------------------------------- def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{  const Value *Src;  const PointerType *PT;  if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&      (PT = dyn_cast<PointerType>(Src->getType())))    return PT->getAddressSpace() == PTX::GLOBAL;  return false; }]>; def load_cons...

...that contains pattern fragment that uses an immediate value to be selected before the immediate instruction itself. So, my question is this, is there anyway to force the ordering of how the instructions get selected. For example, take this pattern (A & B) | (C & ~B), I have the following PatFrag: /// Pattern 1: (lhs & bitpat) | (rhs & ~bitpat) def bfi_pat1 : PatFrag<(ops node:$lhs, node:$rhs, node:$bitpat), (or (and node:$lhs, node:$bitpat), (and node:$rhs, (not node:$lhs)))>; def BFI_i32 : ThreeInOneOut<IL_OP_BFI, (outs GPRI32:$dst), (ins GPRI32:$lhs, GP...

...ockquote> The error here is due to the fact that the 'not' dag is defined as a pattern fragment rather than being an explicit dag node in itself.<br> <br> As a result, you'd need to define your multiclass as:<br> <br> multiclass PTX_LOGIC_20P<string opcstr, PatFrag opnode> { ... }<br> <br> This will correctly match the opnode, though it'll depend on the other 2-operand logic instructions whether this is how it should be done. If you look at the definitions in include/Target/TargetSelectionDAG.td, you'll see which instructions are define...

Hi, Justin > We're been writing multiclasses for each unique type of instruction. The > current PTX_LOGIC version is for 3-operand instructions. A new multiclass > needs to be created for 2-operand logic instructions. I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> { def ripreds :

For reference, here is how the SPU port is using code and pattern fragments: // Holder of code fragments (you'd think this'd already be in // a td file somewhere... :-) class CodeFrag<dag frag> { dag Fragment = frag; } class I64SETCCNegCond<PatFrag cond, CodeFrag compare>: Pat<(cond R64C:$rA, R64C:$rB), (XORIr32 compare.Fragment, -1)>; def : I64SETCCNegCond<setne, I64EQr64>; def : I64SELECTNegCond<setne, I64EQr64>; Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum

...how the SPU port is using code and pattern fragments: >> >> // Holder of code fragments (you'd think this'd already be in >> // a td file somewhere... :-) > > And this comment makes me think, shouldn't this class CodeFrag be > included in the same place where PatFrag is declared: > > ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag ops, > dag frag, code pred = [{}], > > such that we get it included through "llvm/Target/Target.td"? > > I will prepare a patch for this. > Please see the attached patch. Ok to...

Hi Micah, On Tue, Jun 19, 2012 at 6:29 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > If the patterns only include SDNodes, then pattern fragments will work. > > I might be wrong, but I've yet to find a way to do it with machine instructions, which is what you seem to have here. I found in the Cell SPU port: lib/Target/CellSPU/SPUMathInstr.td some examples using code

...ern > fragments: > >> > >> // Holder of code fragments (you'd think this'd already be in // a > td > >> file somewhere... :-) > > > > And this comment makes me think, shouldn't this class CodeFrag be > > included in the same place where PatFrag is declared: > > > > ./include/llvm/Target/TargetSelectionDAG.td:544:class PatFrag<dag > ops, > > dag frag, code pred = [{}], > > > > such that we get it included through "llvm/Target/Target.td"? > > > > I will prepare a patch for this. >...

...about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition. Working backwards from here, the actual PatFrags passed into this are things like ‘mgatherv4i32’. These are patterns that match a MaskedGatherSDNode for a particular data type. MaskedGatherSDNode is the generic SD node that represents a pre...

...e value to be selected before the > immediate instruction itself. > > > > So, my question is this, is there anyway to force the ordering of how the > instructions get selected. > > > > For example, take this pattern (A & B) | (C & ~B), I have the following > PatFrag: > > /// Pattern 1: (lhs & bitpat) | (rhs & ~bitpat) > > def bfi_pat1 : PatFrag<(ops node:$lhs, node:$rhs, node:$bitpat), > >     (or > >      (and node:$lhs, node:$bitpat), > >      (and node:$rhs, (not node:$lhs)))>; > > def BFI_i32 : ThreeInOneOu...

...code. I can match against the load and generate a store instruction, but I need to emit a conversion instruction instead based on the src and dst data types. Any idea where I would pattern this without having to custom lower the load instruction? Here is my current pattern: def generic_load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ return isGenericLoad(dyn_cast<LoadSDNode>(N)); }]>; def ADDRf : ComplexPattern<i32, 2, "SelectADDRf", [frameindex], []>; // Load Memory Operations multiclass LOADm<string asm, PatFrag OpNode, ComplexPattern addr> {...

...itself. > > > > > > > > So, my question is this, is there anyway to force the ordering of how > the > > instructions get selected. > > > > > > > > For example, take this pattern (A & B) | (C & ~B), I have the > following > > PatFrag: > > > > /// Pattern 1: (lhs & bitpat) | (rhs & ~bitpat) > > > > def bfi_pat1 : PatFrag<(ops node:$lhs, node:$rhs, node:$bitpat), > > > >     (or > > > >      (and node:$lhs, node:$bitpat), > > > >      (and node:$rhs, (not node...

Hi, I implemented a pattern matching of the dot product for arm64 and it seemed to work well for the basic case, i.e., class mulB<SDPatternOperator ldop> : PatFrag<(ops node:$Rn, node:$Rm, node:$offset), (mul (ldop (add node:$Rn, node:$offset)), (ldop (add node:$Rm, node:$offset)))>; class mulBz<SDPatternOperator ldop> : PatFrag<(ops node:$Rn, node:$Rm), (mul (ldop node:$Rn), (ldop node:$Rm))>; class Dot...

...reePattern(llvm::Init*, llvm::StringRef): Assertion `New->getNumTypes() == 1 && "FIXME: Unhandled"' failed." Can somebody help me with the code below responsible for this error? // From llvm/lib/Target/X86/X86InstrFragmentsSIMD.td def mgatherv128i16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), (masked_gather node:$src1, node:$src2, node:$src3) , [{ if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N)) return (mgNode->getIndex().getValueType() == MVT::v128i16 || mgNode->getBasePtr(...

...: Cannot specify a transform function for a non-input value! Here the tblgen pattern looks like this: [(set VR256:$dst, (v4i64 (vperm2f128:$src3 VR256:$src1, (v4i64 (memop addr:$src2)))))], and verpm2f128 is defined as: def vperm2f128 : PatFrag<(ops node:$src1, node:$src2), (vector_shuffle node:$src1, node:$src2), [{ return X86::isVPERM2F128Mask(cast<ShuffleVectorSDNode>(N)); }], SHUFFLE_get_vperm2f128_imm>; I don't understand completely how the new system all works. Take a simple SHUFPS match: def SHUFPSrri :...