llvm dev - Dec 2011 - [LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)

RegScavenger is complaining about use of an undefined register, CTR8, in
the BCTR8 instruction, in the following instance (this is from the PPC
backend):

BB#38: derived from LLVM BB %for.end50
    Predecessors according to CFG: BB#36
        %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
        %X4<def> = RLDICR %X3<kill>, 3, 60
        %X5<def> = LI8 <jt#0>[TF=4]
        %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
        %X4<def> = LDX %X4<kill>, %X5<kill>;
mem:LD8[JumpTable]
        MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
        BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
BB#25 BB#12 BB#16 BB#18 BB#13 BB#17

How could CRT8 be marked implicitly-defined and also dead in the same
instruction when it is clearly used in the next instruction? The code
that inserts these instructions is in SDNode
*PPCDAGToDAGISel::Select(SDNode *N) and reads:

  case ISD::BRIND: {
    // FIXME: Should custom lower this.
    SDValue Chain = N->getOperand(0);
    SDValue Target = N->getOperand(1);
    unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR :
PPC::MTCTR8;
    unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR :
PPC::BCTR8;
    Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
                                           Chain), 0);
    return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
  }

Thanks in advance,
Hal

On Mon, 2011-12-05 at 13:14 -0600, Hal Finkel wrote:
> On Mon, 2011-12-05 at 10:12 -0800, Jakob Stoklund Olesen wrote:
> > On Dec 5, 2011, at 9:55 AM, Hal Finkel wrote:
> > 
> > > Author: hfinkel
> > > Date: Mon Dec  5 11:55:17 2011
> > > New Revision: 145819
> > > 
> > > URL: http://llvm.org/viewvc/llvm-project?rev=145819&view=rev
> > > Log:
> > > enable PPC register scavenging by default (update tests and
remove some FIXMEs)
> > 
> > Nice!
> > 
> > Did you run extensive tests with this change?
> 
> Not extensive; I ran the regression tests and a few other files I've
> been using recently. I'll be setup soon to run the test suite on ppc64,
> and so I'll test more-extensively using the test suite. Unfortunately,
> there are still other problems that I have to fix first (like PR11476,
> which may be related to register scavenging, but was not fixed by these
> changes).
> 
> >  Does it work with -O0?
> 
> Good point, I'll run some more tests (and the test suite) with -O0.
Some
> of the regression tests specify -O0 (like the varargs test, which seemed
> to be fine).
> 
> Thanks again,
> Hal
> 
> > 
> > The register scavenger is notorious for exposing sloppy liveness info
in older targets like PPC. I would expect a number of scavenger assertions.
> > 
> > /jakob
> > 
> 
-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory

On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
> RegScavenger is complaining about use of an undefined register, CTR8, in
> the BCTR8 instruction, in the following instance (this is from the PPC
> backend):
> 
> BB#38: derived from LLVM BB %for.end50
>    Predecessors according to CFG: BB#36
>        %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
>        %X4<def> = RLDICR %X3<kill>, 3, 60
>        %X5<def> = LI8 <jt#0>[TF=4]
>        %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
>        %X4<def> = LDX %X4<kill>, %X5<kill>;
mem:LD8[JumpTable]
>        MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
>        BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
>    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> 
> How could CRT8 be marked implicitly-defined and also dead in the same
> instruction when it is clearly used in the next instruction?
This is the kind of sloppy liveness, I was talking about ;-)

llc -verify-machineinstrs should give you better info.

/jakob

On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen
wrote:
> On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
> 
> > RegScavenger is complaining about use of an undefined register, CTR8,
in
> > the BCTR8 instruction, in the following instance (this is from the PPC
> > backend):
> > 
> > BB#38: derived from LLVM BB %for.end50
> >    Predecessors according to CFG: BB#36
> >        %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> >        %X4<def> = RLDICR %X3<kill>, 3, 60
> >        %X5<def> = LI8 <jt#0>[TF=4]
> >        %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> >        %X4<def> = LDX %X4<kill>, %X5<kill>;
mem:LD8[JumpTable]
> >        MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> >        BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> >    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> > 
> > How could CRT8 be marked implicitly-defined and also dead in the same
> > instruction when it is clearly used in the next instruction?
> 
> This is the kind of sloppy liveness, I was talking about ;-)
Yea, I went looking ;)
> 
> llc -verify-machineinstrs should give you better info.
Thanks!

 -Hal
> 
> /jakob
> 
-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory

On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen
wrote:
> On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
> 
> > RegScavenger is complaining about use of an undefined register, CTR8,
in
> > the BCTR8 instruction, in the following instance (this is from the PPC
> > backend):
> > 
> > BB#38: derived from LLVM BB %for.end50
> >    Predecessors according to CFG: BB#36
> >        %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> >        %X4<def> = RLDICR %X3<kill>, 3, 60
> >        %X5<def> = LI8 <jt#0>[TF=4]
> >        %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> >        %X4<def> = LDX %X4<kill>, %X5<kill>;
mem:LD8[JumpTable]
> >        MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> >        BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> >    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> > 
> > How could CRT8 be marked implicitly-defined and also dead in the same
> > instruction when it is clearly used in the next instruction?
> 
> This is the kind of sloppy liveness, I was talking about ;-)
> 
> llc -verify-machineinstrs should give you better info.
Unfortunately, this just tells me what I already knew:

*** Bad machine code: Using an undefined physical register ***
- function:    check
- basic block: for.end50 0x2bef428 (BB#38)
- instruction: BCTR8 %CTR8<imp-use>, %RM<imp-use>
- operand 0:   %CTR8<imp-use>
LLVM ERROR: Found 1 machine code errors.

This comes from the following four statements in
PPCDAGToDAGISel::Select; what's wrong here?
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
unsigned Opc = PPC::MTCTR8;
unsigned Reg = PPC::BCTR8;
Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
                                           Chain), 0);
return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);

Thanks again,
Hal
> 
> /jakob
> 
-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory