Displaying 6 results from an estimated 6 matches for "mtctr8".
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mtctr
2011 Dec 06
2
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
...gt; %X4<def> = RLDICR %X3<kill>, 3, 60
> > %X5<def> = LI8 <jt#0>[TF=4]
> > %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> > %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> > MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> > BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> > Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> >
> > How could CRT8 be marked implicitly-def...
2011 Dec 05
3
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
..., <fi#27>; mem:LD8[FixedStack27]
%X4<def> = RLDICR %X3<kill>, 3, 60
%X5<def> = LI8 <jt#0>[TF=4]
%X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
%X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
How could CRT8 be marked implicitly-defined and also dead in the same
instruction when...
2011 Dec 05
0
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
...:LD8[FixedStack27]
> %X4<def> = RLDICR %X3<kill>, 3, 60
> %X5<def> = LI8 <jt#0>[TF=4]
> %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
>
> How could CRT8 be marked implicitly-defined and also dead in the...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13<def> = BDNZ8 %vreg13,
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...3:
Predecessors according to CFG: BB#2
256B %vreg28<def> = LI 0; GPRC:%vreg28
272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17
288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30
304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31
320B B <BB#8>
Successors according to CFG: BB#8
So maybe LiveInterval would need to be updated to support terminators
that define registers? There are also mis-compiles, but I'm hoping that
they all stem f...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...ll>; G8RC:%vreg2
%vreg4<def> = LI 2048; GPRC:%vreg4
%vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2
%vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4
%vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors according to CFG: BB#1
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
<BB#0>;CTRRC8:%vreg12,%vre...