Displaying 11 results from an estimated 11 matches for "ctr8".
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2011 Dec 06
2
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
On Mon, 2011-12-05 at 13:18 -0800, Jakob Stoklund Olesen wrote:
> On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
>
> > RegScavenger is complaining about use of an undefined register, CTR8, in
> > the BCTR8 instruction, in the following instance (this is from the PPC
> > backend):
> >
> > BB#38: derived from LLVM BB %for.end50
> > Predecessors according to CFG: BB#36
> > %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> &g...
2011 Dec 05
3
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
RegScavenger is complaining about use of an undefined register, CTR8, in
the BCTR8 instruction, in the following instance (this is from the PPC
backend):
BB#38: derived from LLVM BB %for.end50
Predecessors according to CFG: BB#36
%X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
%X4<def> = RLDICR %X3<kill>, 3, 60
%X...
2011 Dec 05
0
[LLVMdev] Dead register (was Re: [llvm-commits] [llvm] r145819)
On Dec 5, 2011, at 12:56 PM, Hal Finkel wrote:
> RegScavenger is complaining about use of an undefined register, CTR8, in
> the BCTR8 instruction, in the following instance (this is from the PPC
> backend):
>
> BB#38: derived from LLVM BB %for.end50
> Predecessors according to CFG: BB#36
> %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> %X4<def> = RLDICR %...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...39;t think that the problem was with those functions. Adding support
for BDNZ and friends in those functions just enabled other passes to
start moving the blocks around, and that seems to have exposed problems
of its own. For example, sometimes LiveIntervals asserts with:
register:
%CTR8
clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446:
void llvm::LiveInterval
s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*,
llvm::MachineBasicBlock::iterator, llvm::SlotIndex,
llvm::MachineOperand&, llvm::LiveInt erval&): Assertion
`!isAllocatable(interval.reg) && &q...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote:
> For example, sometimes LiveIntervals asserts with:
> register:
> %CTR8
> clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446:
> void llvm::LiveInterval
> s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*,
> llvm::MachineBasicBlock::iterator, llvm::SlotIndex,
> llvm::MachineOperand&, llvm::LiveInt erval&): Assertion
> `!isAllocatab...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Fri, 8 Jun 2012 08:49:32 -0700
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote:
>
> > For example, sometimes LiveIntervals asserts with:
> > register:
> > %CTR8
> > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446:
> > void llvm::LiveInterval
> > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*,
> > llvm::MachineBasicBlock::iterator, llvm::SlotIndex,
> > llvm::MachineOperand&, llvm::LiveInt erval&): Ass...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13<def> = BDNZ8 %vreg13,
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...>; G8RC:%vreg2
%vreg4<def> = LI 2048; GPRC:%vreg4
%vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2
%vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4
%vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors according to CFG: BB#1
112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
Predecessors according to CFG: BB#0 BB#1
%vreg12<def> = PHI %vreg13, <BB#1>, %vreg11,
<BB#0>;CTRRC8:%vreg12,%vre...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...gt;> rules, but we haven't found the right set yet.
> [We should add this to the docs somewhere].
http://llvm.org/bugs/show_bug.cgi?id=13058
>> Unfortunately, that breaks your TCRETURNri instructions. Sorry!
>
> I'm guessing that I can rewrite TCRETURN to reference CTR/CTR8
> directly. I'll have to try that.
That should be possible, yes.
/jakob
2012 Jun 08
1
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...the right set yet.
>
> > [We should add this to the docs somewhere].
>
> http://llvm.org/bugs/show_bug.cgi?id=13058
>
> >> Unfortunately, that breaks your TCRETURNri instructions. Sorry!
> >
> > I'm guessing that I can rewrite TCRETURN to reference CTR/CTR8
> > directly. I'll have to try that.
>
> That should be possible, yes.
As it turns out, I don't need to (the patterns in question are never
actually used in the current backend).
Furthermore, your suggestion to mark the register classes as
non-allocatable seems to have worked...
2018 Dec 07
2
Should intrinsics llvm.eh.sjlj.setjmp be with isBarrier flag?
...CFG: BB#1
%vreg2<def> = ADDIStocHA %X2, <ga:@env_sigill>;
G8RC_and_G8RC_NOX0:%vreg2
%vreg3<def> = LDtocL <ga:@env_sigill>, %vreg2<kill>; mem:LD8[GOT]
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg2
%vreg4<def> = EH_SjLj_SetJmp64 %vreg3<kill>, %CTR8<imp-def,dead>;
GPRC:%vreg4 G8RC:%vreg3
Currently Powerpc sets EH_SjLj_SetJmp64 with flag isBarrier. But it is also
a fall-through instruction. So it fails in machineinstr verifying.
I checked other platforms like X86 and ARM, they also set this intrinsics
as barrier. For my understanding, a...