Hello,
I'm developing a llvm backend. It seems that, if i16 is not a legal type
(no register can hold i16 types in RegisterInfo.td and as a RegisterClass in
SelLowering.cpp), i16 should be promoted to i32.
Nonotheless, this simple program:
int main(){
volatile short a;
a= 3;
return 0;
}
which is trasformed in this IR:
define i32 @main() nounwind readnone {
entry:
%a = alloca i16, align 2 ; <i16*> [#uses=1]
volatile store i16 3, i16* %a, align 2
ret i32 0
}
fails to compile with the following error:
LLVM ERROR: Cannot yet select: 0x181c2d0: ch = store 0x1204a08, 0x181c248,
0x181be90, 0x181bfa0 <0x12022ec:0> <trunc i16> <volatile>
alignment=2
Can anybody help?
Thanks
Giovanni.
--
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On Jun 23, 2011, at 8:47 AM, Giovanni Ansaloni wrote:> > Hello, > I'm developing a llvm backend. It seems that, if i16 is not a legal type > (no register can hold i16 types in RegisterInfo.td and as a RegisterClass in > SelLowering.cpp), i16 should be promoted to i32.Arithmetic operations will be promoted to the next-smallest legal type (i32 usually). Loads and stores, however, will not. You still need to implement patterns for those. In particular, the extending loads and truncating stores. -Jim> Nonotheless, this simple program: > > int main(){ > volatile short a; > a= 3; > return 0; > } > > which is trasformed in this IR: > > define i32 @main() nounwind readnone { > entry: > %a = alloca i16, align 2 ; <i16*> [#uses=1] > volatile store i16 3, i16* %a, align 2 > ret i32 0 > } > > fails to compile with the following error: > > LLVM ERROR: Cannot yet select: 0x181c2d0: ch = store 0x1204a08, 0x181c248, > 0x181be90, 0x181bfa0 <0x12022ec:0> <trunc i16> <volatile> alignment=2 > > Can anybody help? > Thanks > Giovanni. > > -- > View this message in context: http://old.nabble.com/type-promotion-i16--%3E-i32-tp31911111p31911111.html > Sent from the LLVM - Dev mailing list archive at Nabble.com. > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Hi Giovanni,
How do byte/short loads and stores work on your architecture?
* If you have halfword loads and stores, you need to put patterns for
them in YourInstrInfo.td.
* If you only have word-size loads and stores:
- If you support arbitrary address alignment, put
"setTruncStoreAction(MVT::i32, MVT::i16, Expand);" in the
YourTargetLowering constructor in YourISelLowering.cpp.
- If you have alignment restrictions, define
YourTargetLowering::allowsUnalignedMemoryAccesses() appropriately (see
XCore, ARM, X86 backends for examples). You may also need to define
patterns for {z,s}extloadi{8,16} and truncstorei{8,16} in
YourInstrInfo.td which perform the appropriate address mask, data load,
and shift. I did add these patterns, but am not sure if there's a way
to get the LLVM machinery to do this for you.
-Matt
On 06/23/2011 10:47 AM, Giovanni Ansaloni wrote:> Hello,
> I'm developing a llvm backend. It seems that, if i16 is not a legal
type
> (no register can hold i16 types in RegisterInfo.td and as a RegisterClass
in
> SelLowering.cpp), i16 should be promoted to i32.
> Nonotheless, this simple program:
>
> int main(){
> volatile short a;
> a= 3;
> return 0;
> }
>
> which is trasformed in this IR:
>
> define i32 @main() nounwind readnone {
> entry:
> %a = alloca i16, align 2 ;<i16*> [#uses=1]
> volatile store i16 3, i16* %a, align 2
> ret i32 0
> }
>
> fails to compile with the following error:
>
> LLVM ERROR: Cannot yet select: 0x181c2d0: ch = store 0x1204a08, 0x181c248,
> 0x181be90, 0x181bfa0<0x12022ec:0> <trunc i16>
<volatile> alignment=2
>
> Can anybody help?
> Thanks
> Giovanni.
>