similar to: [LLVMdev] type promotion i16 -> i32

I have created custom Clang flag -no_nop_optimise which can be passes with clang on command line. I am planning to implement someting like: when -no_nop_optimise flag is passed on the command line do not emit a nop instruction. i.e. inside SelLowering class if ( !OPT_no_nop_optimise) { BuildMI(*BB, MI, DL, TII->get(Mips::NOP)); } Any clues on how can I pass the flag to the LLVM backend

hello, i'm pete ,how can i order rows of matrix by max to min value? I have a matrix of membership degrees, with 82 (i) rows and K coloumns, K are clusters. I need first and second largest elements of the i-th row. for example 1 0.66 0.04 0.01 0.30 2 0.02 0.89 0.09 0.00 3 0.06 0.92 0.01 0.01 4 0.07 0.71 0.21 0.01 5 0.10 0.85 0.04 0.01 6 0.91 0.04 0.02 0.02 7 0.00 0.01 0.98 0.00 8 0.02

Reframing and Reposting my earlier query: My target has 16-bit registers for indirect address of data. All other registers are 8-bit. Therefore I have added regclasses for i8 and i16 types. All arithmetic operations (including pointer arithmetic ) are 8-bit operations. The problem is that LLVM does not expand i16 operations to i8 operations in presence of i16 regclass. What is the best way to

Is there a way to force llvm to promote all smaller types to i32 instead of i16? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Tue, Feb 3, 2009 at 10:23 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Is there a way to force llvm to promote all smaller types to i32 instead of > i16? It should just work if i16 is also set to promote... what are you trying to do? -Eli

I want to promote i1 to i32 and not i16 as i32 is my native type and i16 is emulated, but I need to handle i16 as a special case so I don't want to promote it. I will see if what Bill pointed out is what I need. Micah -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Tuesday, February 03, 2009 11:08 AM To:

hi, either function call in this code makes llc (targeting SPU) assert: declare i8 @return_i8() declare i16 @return_i16() define void @testfunc() { %rv1 = call i8 @return_i8() %rv2 = call i16 @return_i16() ret void } Attached is a patch to fix it, and remove some related redundant code. Does this rather trivial fix warrant a test case? kalle -------------- next part -------------- A

"Villmow, Micah" <Micah.Villmow at amd.com> writes: > Sorry, <4 x i8> should convert to a <1 x i32>. Why? I'm really confused. Shouldn't this converts to a <4 x i32>? -Dave

The comments in the code state it should do bitcast, op, then bitcast, not extend, op and truncate. "SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { // Vector "promotion" is basically just bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64." So following the same logic <4 x i8> bitcasts into a

Micah, I think that your patch is missing the necessary modifications in lib/VMCore/ValueTypes.cpp to EVT::getEVTString() and EVT::getTypeForEVT. -Hal On Fri, 27 Jul 2012 22:54:24 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Vector promotion which is new in LLVM 3.1 is broken for sub32 bit > types. The problem is in the VectorLegalizer::PromoteVectorOp. The

Hi, I'm working on an LLVM backend for an architecture which does not natively support half-word loads. I'm having trouble getting LLVM to promote i16 to i32 loads for me - should I expect LLVM to be able to do this, are do I have to write a custom lowerer? This post (http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/019929.html) gave me the impression that it should be possible,

If I have an '&' operator inside an 'if' statement, LLVM seems to always promote a 16 bit integer type to a 32 bit integer type. I don't want this to happen because my back-end only supports 16 bit types. Why is this happening? Where might this be happening, so I can fix it? It doesn't seem to happen with the '|' operator, only '&'. Thanks!

I think that you attached the wrong patch. The attached patch is the one which adds the new MVT types. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Saturday, July 28, 2012 01:54 To: Developers Mailing List Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> Vector promotion which is new in LLVM 3.1 is broken for

In my language there are a lot of i16 definitions, but almost all of the time they are upgraded to i32 because my add operations only happen on i32. So to be representative to my language definition, I have a lots of Sext/Zext and Truncs pretty much every time I add or subtract. As soon as I pass through InstCombine things look much nicer, all the upcasts and downcasts go away, but my test cases

After ordering the table of membership degrees , i must get the difference between the first and second coloumns , between the first and second largest membership degree of object i. This for K=2,K=3,....to K.max=6. This difference is multiplyed by the Crisp silhouette index vector (si). Too it dependending on K=2,...,K.max=6; the result divided by the sum of these differences I need a final

Micah, One more thing ;) -- llvm::getEnumName in utils/TableGen/CodeGenTarget.cpp -Hal On Tue, 31 Jul 2012 21:02:02 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Ahh yep, thanks for catching that, new patch attached. > > > -----Original Message----- > > From: Hal Finkel [mailto:hfinkel at anl.gov] > > Sent: Tuesday, July 31, 2012 1:40 PM

Hi, SystemZ supports @llvm.ctlz.i64() natively with a single instruction (FLOGR), and lesser bitwidth versions of the intrinsic are promoted to i64. For some reason, this leads to unfolded additions of constants as shown below: This function: define i16 @fun(i16 %arg) {   %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)   ret i16 %1 } ,gives this optimized DAG as input to instruction

>Though I am having trouble in understanding how  x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as >far as I can tell. The Type-Legalizer can handle vector types in the following ways: 1. Split - this splits vectors into two halves. For example on SSE4, <4 x i64> is split to <2 x i64> 2.

Hello, I'm Carla, an italian student, I'm looking for a package to transform non normal data to normality. I tried to use Box Cox, but it's not ok. There is a package to use Johnson families' transormation? Can you give me any suggestions to find free software as R that use this trasform? Thank yuo very much Carla ____________________________________________________________ 6X

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp. The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues. This can be reproduced by setting in