llvm dev - Jan 2010 - [LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz

On 15 Jan 2010, at 18:03, Chris Lattner wrote:
> On Jan 14, 2010, at 10:13 PM, David Conrad wrote:
> 
>> Other targets that I know of that could potentially benefit from  
>> this optimization being global (that have a clz and bitreverse  
>> instruction but not ctz) are AVR32 and C64x, neither of which llvm  
>> has backends for yet.
> 
> When/if another target wants this, we could add a ISD::RBIT operation,  
> it doesn't need to be added at the llvm ir level,
The XCore also has ctlz and bitreverse instructions and not cttz. At the moment
in the XCore backend cttz is marked as legal and expanded to this pair of
instructions in a pattern in the InstrInfo.td.

-- 
Richard Osborne | XMOS
http://www.xmos.com

On Jan 15, 2010, at 11:37 AM, Richard Osborne wrote:
>
> On 15 Jan 2010, at 18:03, Chris Lattner wrote:
>
>> On Jan 14, 2010, at 10:13 PM, David Conrad wrote:
>>
>>> Other targets that I know of that could potentially benefit from
>>> this optimization being global (that have a clz and bitreverse
>>> instruction but not ctz) are AVR32 and C64x, neither of which llvm
>>> has backends for yet.
>>
>> When/if another target wants this, we could add a ISD::RBIT  
>> operation,
>> it doesn't need to be added at the llvm ir level,
>
> The XCore also has ctlz and bitreverse instructions and not cttz. At  
> the moment in the XCore backend cttz is marked as legal and expanded  
> to this pair of instructions in a pattern in the InstrInfo.td.
In that case, perhaps it makes sense to add it as an ISD::RBIT  
operation straight away.

The rest of the patch looks good to me.

-Jim

On Jan 15, 2010, at 2:52 PM, Jim Grosbach wrote:
> 
> On Jan 15, 2010, at 11:37 AM, Richard Osborne wrote:
> 
>> 
>> On 15 Jan 2010, at 18:03, Chris Lattner wrote:
>> 
>>> On Jan 14, 2010, at 10:13 PM, David Conrad wrote:
>>> 
>>>> Other targets that I know of that could potentially benefit
from
>>>> this optimization being global (that have a clz and bitreverse
>>>> instruction but not ctz) are AVR32 and C64x, neither of which
llvm
>>>> has backends for yet.
>>> 
>>> When/if another target wants this, we could add a ISD::RBIT  
>>> operation,
>>> it doesn't need to be added at the llvm ir level,
>> 
>> The XCore also has ctlz and bitreverse instructions and not cttz. At  
>> the moment in the XCore backend cttz is marked as legal and expanded  
>> to this pair of instructions in a pattern in the InstrInfo.td.
> 
> In that case, perhaps it makes sense to add it as an ISD::RBIT  
> operation straight away.
Since only a couple of targets can use this, it shouldn't block this patch
from going in. Jim, can you commit this?

Thanks,

Evan
> 
> The rest of the patch looks good to me.
> 
> -Jim
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev