search for: ctz

Displaying 14 results from an estimated 14 matches for "ctz".

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2019 Feb 20
2
proposal for optimization method
...0)) return 0;// invalid parameters uint64_t mask; if (bits == 64) mask = -1; else { mask = 1; mask<<=bits; mask--; } x&=mask; uint64_t result=1, state=x, ctz=0; while(state!=1ULL) { ctz=__builtin_ctzll(state^1); result|=1ULL<<ctz; state+=x<<ctz; state&=mask; } return result; } now consider the following steps: from the 2 constants (d and r) w...
2010 Jan 15
4
[LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz
...nk of doing it was to add a bitreverse intrinsic to llvm ir, which itself might not be the best option since bitreverse probably isn't too common. Other targets that I know of that could potentially benefit from this optimization being global (that have a clz and bitreverse instruction but not ctz) are AVR32 and C64x, neither of which llvm has backends for yet. -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-ctz-arm.diff Type: application/octet-stream Size: 5160 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/2...
2010 Jan 15
2
[LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz
On 15 Jan 2010, at 18:03, Chris Lattner wrote: > On Jan 14, 2010, at 10:13 PM, David Conrad wrote: > >> Other targets that I know of that could potentially benefit from >> this optimization being global (that have a clz and bitreverse >> instruction but not ctz) are AVR32 and C64x, neither of which llvm >> has backends for yet. > > When/if another target wants this, we could add a ISD::RBIT operation, > it doesn't need to be added at the llvm ir level, The XCore also has ctlz and bitreverse instructions and not cttz. At the moment...
2010 Jan 15
0
[LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz
...treverse > probably isn't too common. I haven't looked at the patch in detail, but this approach makes sense to me. > Other targets that I know of that could potentially benefit from > this optimization being global (that have a clz and bitreverse > instruction but not ctz) are AVR32 and C64x, neither of which llvm > has backends for yet. When/if another target wants this, we could add a ISD::RBIT operation, it doesn't need to be added at the llvm ir level, -Chris
2009 Jun 12
2
[LLVMdev] Proposal for pluggable intrinsics
...cks to guarantee memory-safety of programs. SAFECode needs to insert checks into the programs (say, please check this load instruction for me). Currently SAFECode inserts these checks as normal call instructions. It would be great that LLVM can treat them as first-class intrinsics (like "llvm.ctz"), which have additional semantics and could be lowered as ordinary function calls in subsequent passes. This would be very useful because 1) It simplifies the analysis logic 2) LLVM can apply out-of-box compiler optimization technique way more easily on these programs (for example, SAFECode...
2010 Jan 15
0
[LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz
...an 2010, at 18:03, Chris Lattner wrote: > >> On Jan 14, 2010, at 10:13 PM, David Conrad wrote: >> >>> Other targets that I know of that could potentially benefit from >>> this optimization being global (that have a clz and bitreverse >>> instruction but not ctz) are AVR32 and C64x, neither of which llvm >>> has backends for yet. >> >> When/if another target wants this, we could add a ISD::RBIT >> operation, >> it doesn't need to be added at the llvm ir level, > > The XCore also has ctlz and bitreverse instructi...
2010 Jan 18
1
[LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz
...attner wrote: >> >>> On Jan 14, 2010, at 10:13 PM, David Conrad wrote: >>> >>>> Other targets that I know of that could potentially benefit from >>>> this optimization being global (that have a clz and bitreverse >>>> instruction but not ctz) are AVR32 and C64x, neither of which llvm >>>> has backends for yet. >>> >>> When/if another target wants this, we could add a ISD::RBIT >>> operation, >>> it doesn't need to be added at the llvm ir level, >> >> The XCore also has...
2009 Jun 12
0
[LLVMdev] Proposal for pluggable intrinsics
...FECode needs to insert > checks > into the programs (say, please check this load instruction for me). Hi. > Currently SAFECode inserts these checks as normal call instructions. > It > would be great that LLVM can treat them as first-class intrinsics > (like > "llvm.ctz"), which have additional semantics and could be lowered as > ordinary function calls in subsequent passes. I was just about to recommend using normal function calls :). > This would be very useful because 1) It simplifies the analysis > logic 2) > LLVM can apply out-of-box comp...
2010 Jan 15
1
[LLVMdev] [PATCH] Emit rbit, clz on ARM for __builtin_ctz
...isn't too common. > > I haven't looked at the patch in detail, but this approach makes sense > to me. > >> Other targets that I know of that could potentially benefit from >> this optimization being global (that have a clz and bitreverse >> instruction but not ctz) are AVR32 and C64x, neither of which llvm >> has backends for yet. > > When/if another target wants this, we could add a ISD::RBIT operation, > it doesn't need to be added at the llvm ir level, Bit reversal turns up in most FFT algorithms, so it wouldn't hurt to be able to...
2009 Jun 12
0
[LLVMdev] Tablegen question
On Jun 9, 2009, at 1:16 PM, Manjunath Kudlur wrote: >> All of the tablegen backends work this way. As you mentioned, >> >> there are no target-specific tablegen backends at present. >> >> >> >> The underlying observation here is that features are never >> >> fundamentally "specific for a target". For example, a mapping >>
2009 Jun 09
2
[LLVMdev] Tablegen question
> All of the tablegen backends work this way. As you mentioned, > there are no target-specific tablegen backends at present. > > The underlying observation here is that features are never > fundamentally "specific for a target". For example, a mapping > between vector opcodes and associated scalar opcodes could > reasonably be made on many architectures. Even >
2014 Jan 06
5
[LLVMdev] LLVM Weekly - #1, Jan 6th 2014
...m of errors covering the rest of the input file. It now recognises this error and presents a single error <http://llvm-reviews.chandlerc.com/rL198540>. ## Other project commits * Building libclc with LLVM 3.5 was fixed <http://llvm-reviews.chandlerc.com/rL198167> * In libcxx, the clz/ctz family of functions are now implemented for when building with Visual C++ on Win32 or Win64. <http://llvm-reviews.chandlerc.com/rL198481> * The PollyCananicalizePass was introduced. This is a ModulePass that schedules the Polly canonicalization passes. <http://llvm-reviews.chandlerc.com/r...
2016 May 03
3
Reasoning about known bits of the absolute value of a signed integer
I'm trying to reason about how to find certain bit positions of the absolute value of a given integer value. Specifically, I want to know the highest possibly set bit and lowest possibly set bit of the absolute value, in order to find the range between the two. Note that I'm specifically trying to be as conservative as possible. This is what I have so far: If the sign bit of the
2020 Feb 27
2
[PATCH] Update the 5 year logo to 10 year logo
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