search for: xcore

Hi Eric, Could you explain the intent and policy regarding the test-suite body of code. Should the test be left as much as possible as-is (even if technically incorrect)? Should changes only affect the XCore target (#ifdef) or should all targets get the changes? Taking "int32_t main" as an example. The correct return type & argc for main is 'int'. In the XCore tool chain, 'int32_t' equates to long (IIRC) and hence is not acceptable in the type signature for main. Should t...

... and so (I infer from that) it should not be patched let alone need any changes. Assuming my inference is correct, any patching should only affect the XCore target and only if there is a good reason why the XCore requires the change. So, is #ifdef around all/most changes the correct way to submit a patch? Robert ________________________________ From: Eric Christopher [echristo at gmail.com] Sent: 13 January 2014 20:24 To: Robert Lytton; llvmdev at c...

Hello all. At XMOS we are working towards updating the upstream XCore backend for newer versions of the chip. XCore is the XMOS processor. The XCore backend was written by Richard Osborne at XMOS. Richard has moved on. The current code owner in CODE_OWNERS.TXT, Robert Lytton, has also moved on. For some years XMOS has developed the compiler in-house, for new versio...

Hi, I have found it necessary to make some changes to the test-suite for the XCore platform. These changes include: altering #includes, as supported by XCore; using stdout or stderr to make the output diffs consistent (fixing expected output too); (This work is still under review as best way to do it) 'fixing' symbol and type problems e.g name clashes...

Hi again, Now, after I fixed the graph coloring regalloc bug that was triggered by the ARM target, I continue testing and found another bug, this time on the XCore target. First I thought that it is again specific to my register allocator, but it seems to be trigerred also by LLVM's linearscan register allocator. I don't know if the XCore target is stable enough in LLVM, or may be I should just safely skip it during testing because it is not mature y...

Hi XCore and PIC16 maintainers, I'd appreciate it if you guys could move your AsmPrinter implementation to be in a subdirectory like the rest of the other targets (e.g. make it live in lib/Target/PIC16/AsmPrinter). Anton is planning to move MSP430 to use the same approach. Having all the targ...

...AM, Richard Osborne <richard at xmos.com> wrote: > Roman Levenstein wrote: >> Hi again, >> >> Now, after I fixed the graph coloring regalloc bug that was triggered >> by the ARM target, I continue testing and found another bug, this >> time >> on the XCore target. First I thought that it is again specific to my >> register allocator, but it seems to be trigerred also by LLVM's >> linearscan register allocator. >> >> I don't know if the XCore target is stable enough in LLVM, or may >> be I >> should just s...

...: > > >> Roman Levenstein wrote: >> >>> Hi again, >>> >>> Now, after I fixed the graph coloring regalloc bug that was triggered >>> by the ARM target, I continue testing and found another bug, this >>> time >>> on the XCore target. First I thought that it is again specific to my >>> register allocator, but it seems to be trigerred also by LLVM's >>> linearscan register allocator. >>> >>> I don't know if the XCore target is stable enough in LLVM, or may >>> be I &g...

Hi Richard, Thanks for working on this! Your patched solved my initial problem, but introduced another one. Please find attached another BC file that fails on xcore with the linear scan regalloc. This is the error message I get eliminateFrameIndex Frame size too big: -3 0 llc 0x08affd1e 1 libc.so.6 0xb7d35a01 abort + 257 2 llc 0x081a0972 llvm::XCoreRegisterInfo::eliminateFrameIndex(llvm::ilist_iterator<llvm::MachineInstr>, int, llvm::R...

> Chris Lattner wrote: > >> Hi XCore and PIC16 maintainers, >> >> I'd appreciate it if you guys could move your AsmPrinter >> implementation to be in a subdirectory like the rest of the other >> targets (e.g. make it live in lib/Target/PIC16/AsmPrinter). >> I've moved the XCore AsmPrinter...

Roman Levenstein wrote: > Hi again, > > Now, after I fixed the graph coloring regalloc bug that was triggered > by the ARM target, I continue testing and found another bug, this time > on the XCore target. First I thought that it is again specific to my > register allocator, but it seems to be trigerred also by LLVM's > linearscan register allocator. > > I don't know if the XCore target is stable enough in LLVM, or may be I > should just safely skip it during testing be...

On Jan 14, 2009, at 3:14 AM, Richard Osborne wrote: >> Evan > OK, that make sense, I'll take a look at changing this. I've added a > bug > for the issue: > > http://llvm.org/bugs/show_bug.cgi?id=3324 > > There is currently no Backend: XCore component in bugzilla so I've put > it under new-bugs. Could someone add this component for me. Added. You should also be automatically CC'd on anything filed to that component, -Chris

..., Matt Johnson wrote: > Hi All, > Some targets don't provide subword (e.g., i8 and i16 for a 32-bit > machine) load and store instructions, so currently we have to > custom-lower Load- and StoreSDNodes in our backends. For examples, see > LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I > believe it's possible to support this lowering in a target-agnostic > fashion in LegalizeDAG.cpp, similar to what is done for > non-naturally-aligned loads and stores using the > allowsUnalignedMemoryAccesses() target hook. The XCore does support...

...Osborne wrote: > > >>> Evan >>> >> OK, that make sense, I'll take a look at changing this. I've added a >> bug >> for the issue: >> >> http://llvm.org/bugs/show_bug.cgi?id=3324 >> >> There is currently no Backend: XCore component in bugzilla so I've put >> it under new-bugs. Could someone add this component for me. >> > > Added. You should also be automatically CC'd on anything filed to > that component, > > -Chris > Thanks, I've just commited a fix in r62238:...

Roman Levenstein wrote: > Hi Richard, > > Thanks for working on this! Your patched solved my initial problem, > but introduced another one. Please find attached another BC file that > fails on xcore with the linear scan regalloc. > > This is the error message I get > eliminateFrameIndex Frame size too big: -3 > 0 llc 0x08affd1e > 1 libc.so.6 0xb7d35a01 abort + 257 > 2 llc 0x081a0972 > llvm::XCoreRegisterInfo::eliminateFrameIndex(llvm::ilist_iterator<ll...

Chris Lattner wrote: > Hi XCore and PIC16 maintainers, > > I'd appreciate it if you guys could move your AsmPrinter > implementation to be in a subdirectory like the rest of the other > targets (e.g. make it live in lib/Target/PIC16/AsmPrinter). > Hi Chris, I'll try to get this done either this week...

Hi All, Some targets don't provide subword (e.g., i8 and i16 for a 32-bit machine) load and store instructions, so currently we have to custom-lower Load- and StoreSDNodes in our backends. For examples, see LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I believe it's possible to support this lowering in a target-agnostic fashion in LegalizeDAG.cpp, similar to what is done for non-naturally-aligned loads and stores using the allowsUnalignedMemoryAccesses() target hook. I wanted to see if there was any inter...

Chris, I will try to get it done before 2.6. (8/21). - Sanjiv -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu on behalf of Chris Lattner Sent: Wed 8/12/2009 10:08 PM To: LLVM Developers Mailing List Subject: [LLVMdev] XCore & PIC16 AsmPrinters Hi XCore and PIC16 maintainers, I'd appreciate it if you guys could move your AsmPrinter implementation to be in a subdirectory like the rest of the other targets (e.g. make it live in lib/Target/PIC16/AsmPrinter). Anton is planning to move MSP430 to use the sa...

I'd like to be Code owner for the XCore backend if no one objects Thanks, Richard -- Richard Osborne | XMOS http://www.xmos.com

On Mar 1, 2010, at 4:09 PM, Richard Osborne wrote: > On 01/03/10 21:14, Chris Lattner wrote: >> On Mar 1, 2010, at 10:52 AM, Richard Osborne wrote: >> >>> On 23/02/10 14:58, Richard Osborne wrote: >>> >>>> I've recently changed the XCore target to implement BR_JT as a jump to a >>>> series jumps. The jump table entries are expand inline in the function >>>> so there is no longer a need to emit jump tables at the end of the >>>> function. However the emission of jump tables at the end of a functio...