llvm dev - Nov 2009 - [LLVMdev] how to define a 24-bits register class

hi every one,

i have a very strange cpu that have 24-bits reigsters, but i cant see
i24 in machine value type? and if defining it as MVT others will be
ok?


thank you very much

On Nov 13, 2009, at 6:45 AM, ether zhhb wrote:
> hi every one,
>
> i have a very strange cpu that have 24-bits reigsters, but i cant see
> i24 in machine value type? and if defining it as MVT others will be
> ok?
You'd want to add a new i24 MVT enum.

-Chris

On Friday, November 13, 2009 11:29 AM, Chris Lattner
wrote:
> 
> On Nov 13, 2009, at 6:45 AM, ether zhhb wrote:
> 
> > hi every one,
> >
> > i have a very strange cpu that have 24-bits reigsters, but 
> i cant see
> > i24 in machine value type? and if defining it as MVT others will be 
> > ok?
> 
> You'd want to add a new i24 MVT enum.
Can this be done without breaking the other code generators? I recently
tried going down this path for a back end that I'm working on and I
found that it caused virtually all of the tests for the other code
generators to fail. I have to admit that I didn't dig too deeply to
figure out what was causing the failures. Once I realized that fixing it
would require modifying the other back ends, I figured I should find a
different solution.

What I came up with was to define some ValueTypes of type 'Other' in the
sizes that I need in my MyTarget.td file, like so:

  class MyTargetValueType<int size> : ValueType<size, 0> {
    string Namespace = "MyTargetMVT";
  }

  def i24 : MyTargetValueType<24>;
  def i48 : MyTargetValueType<48>;
  def i56 : MyTargetValueType<56>;

I haven't reached the point yet where I'm using these in instruction
selection, so I have no idea whether this approach will actually work,
but for the time being it seems to be. And it doesn't require any
modifications to the other code generators.

Is this a better solution? Or a dead end?

-Ken