search for: reigsters

hi every one, i have a very strange cpu that have 24-bits reigsters, but i cant see i24 in machine value type? and if defining it as MVT others will be ok? thank you very much

On Nov 13, 2009, at 6:45 AM, ether zhhb wrote: > hi every one, > > i have a very strange cpu that have 24-bits reigsters, but i cant see > i24 in machine value type? and if defining it as MVT others will be > ok? You'd want to add a new i24 MVT enum. -Chris

Now I am trying to use LLVM to write a simulator and take LLVM as IR to dynamic translate machine code, I encounter some issues when try to write some IR to express writting a value to the reigster. The situation is described as the following description. write_reg is my function for writing "v" to the register indicated by "index". ptr_gpr is the struct pointer for my

The Wine development release 1.9.20 is now available. What's new in this release (see below for details): - Reimplementation of the clipboard API. - Message handling in WebServices. - Many more API Set libraries. - Various bug fixes. The source is available from the following locations: http://dl.winehq.org/wine/source/1.9/wine-1.9.20.tar.bz2

https://bugs.freedesktop.org/show_bug.cgi?id=60680 Priority: medium Bug ID: 60680 Assignee: nouveau at lists.freedesktop.org Summary: HDMI is connected and has mode, TV says "no signal" QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: Linux (All) Reporter:

I am submitting the patch which supports more Capability Structures and Device Specific Registers for passthrough device. In Xen 3.3 unstable, qemu-dm supports Configuration Header, MSI Capability Structure, and MSI-X Capability Structure. But qemu-dm does not support PCI Express Capability Structure, Device Specific Registers, etc (writing them is ignored). To support various I/O devices, I