search for: mytarget

...ate the formula based on the passed in field name, but I'm struggling to create a vector based in that field. for example if I hard code with the actual field name Y = df$Target, everything works fine. but if I use the passed in parameter name, it doesn't give me what I want, Y = df$mytarget Here is the function, # trying to pass field name to a function logistictest <- function(df,mytarget) { #library for AUC calculation library(caTools) #build logistic model mytarget <- deparse(substitute(mytarget)) myformula <- paste(mytarget," ~ .") myformula <-...

...create the formula based on the passed in field name, but I'm struggling to create a vector based in that field. for example if I hard code with the actual field name Y = df$Target, everything works fine. but if I use the passed in parameter name, it doesn't give me what I want, Y = df$mytarget Here is the function, # trying to pass field name to a function logistictest <- function(df,mytarget) { #library for AUC calculation library(caTools) #build logistic model mytarget <- deparse(substitute(mytarget)) myformula <- paste(mytarget," ~ .") myformula <- deparse(...

...nstruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class mytarget::ARegsRegClass unsigned ScratchReg = MF.getRegInfo().createVirtualRegister(&mytarget::ARegsRegClass); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); BuildMI(*MI.getParent(), II, dl, TII.get(mytarget::ADD_AReg), ScratchReg).addReg(FramePtr).addImm(Offset); // Update the origina...

I am working on implementing a new target for llvm. So far (to make debugging easier), I was compiling a C code into 2 steps: 1) generate the llvm file: clang -ccc-host-triple mytarget -emit-llvm -S myfile.c -o myfile.ll 2) generate the assembly file using llc -march=mytarget myfile.ll Sometimes, I add some verbosity for the 2nd command like "-print-after-all". Now, I'd like to compile a C code in 1 step using clang (clang -ccc-host-triple mytarge -S myfile.c -o my...

Hi, Is there a way to see what the default argument llc takes from clang/clang++ ? I'm debugging my backend with a very simple c++ program. Running through *clang++ -target myTarget -S simple.cpp -o simple.s * (bug does no show up) gives me different results from *clang++ -target myTarget -S -emit-llvm -o simple.cpp -o simple.ll* *llc simple.ll -o simple.s *(bug shows up) Just trying to understand what's the difference here Thanks, Patrick -------------- next part ----...

I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've created an initial MyTargetSchedule.td def MyTargetModel : SchedMachineModel { // HW can decode 2 instructions per cycle. let IssueWidth = 2; let LoadLatency = 4; let MispredictPenalty = 16; // This flag is set to allow the scheduler to assign a default model to // unrecognized opcodes. let CompleteModel = 0;...

Hi Developers, I have written C program and want to generate IR file for Specific Target I have tried with following command but got a error as follows, COMMAND: *clang -S -emit-llvm -march=leg ~/llc-test-examples/ex9.c -o ~/llc-test-examples/ex9.ll* ERROR: *error: unknown target CPU 'leg'* So any please help me what all other step should I do previously to get my *leg* target in clang.

...nterleave.count", i32 1} !6 = distinct !{!6, !2} !7 = distinct !{!7, !4, !5} I get the following error: LLVM ERROR: Cannot select: t21: ch = store<ST64[%6](align=4)> t20, t19, t6, undef:i64 I don't understand why because it seems to me store is specified well in [MyTarget]InstrInfo.td . Can somebody help with an idea? Myself I will try to debug the code generated with TableGen, implementing the function SelectCode() . Best regards, Alex

Hello, Given a TargetRegisterClass *RC, I was wondering if there is a way to find out what register class it is directly, instead of comparing it against all the &mytarget::Class1, &mytarget::Class2 etc. This goes back to my original intention of having special query functions for a subset of register classes. Suppose I wanted vector register classes (more than one, say 2-elements and 4-elements). I want to define special query functions for these classes, like g...

On Feb 16, 2011, at 11:08 AM, Damien Vincent wrote: > I am working on implementing a new target for llvm. > So far (to make debugging easier), I was compiling a C code into 2 steps: > 1) generate the llvm file: > clang -ccc-host-triple mytarget -emit-llvm -S myfile.c -o myfile.ll > 2) generate the assembly file using > llc -march=mytarget myfile.ll > > Sometimes, I add some verbosity for the 2nd command like "-print-after-all". > Now, I'd like to compile a C code in 1 step using clang (clang -ccc-host-triple...

...;me at vk4msl.com> wrote: [...] > The crux of this is that we cannot assume the local IPv4 address is > unique, since it's not (and in many cases, not even static). If the IP address is not significant, you can tell ssh to not record them ("CheckHostIP no"). [...] > Host mytarget > Hostname 172.16.1.2 > ProxyJump user2 at bastion2 I think you just need "HostKeyAlias mytarget" here. -- Darren Tucker (dtucker at dtucker.net) GPG key 11EAA6FA / A86E 3E07 5B19 5880 E860 37F4 9357 ECEF 11EA A6FA Good judgement comes with experience. Unfort...

I've started experimenting with winetricks of the late, but I've run into an issue. Where does winetricks install all of it's files, I can't find them in the location I specified or anywhere else....

I try to define a register class def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] to simulate even/odd pair of GPR32 register. Actually, I just use GPR64 as a temporary register. My CPU just support i32 Integer type directly. I use FDR to save f64. def FDR : RegisterClass<"mytarget", [f64], 64,[FD0, FD1, ....] When I move f64 to eve...

hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<"t0",[R0,R1]>; ... def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] In mytargetISelLowering.cpp: I define i1, i8 , i16 and i32 are legal. 1. I still have problem. I save my function return double  value in R0 ...

....edu> 日期: 2009,331,周二,1:04上午 This is probably instruction selection issue. I would look at the dag at various stafes of isel. Try -view-legalize-type-dags, -view-legalize-dags, etc. Evan On Mar 29, 2009, at 11:54 PM, 任坤 wrote: I try to define a register class def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] to simulate even/odd pair of GPR32 register. Actually, I just use GPR64 as a temporary register. My CPU just support i32 Integer type directly. I use FDR to save f64. def FDR : RegisterClass<"mytarget", [f64], 64,[FD0, FD1, ....] When I move f64 to eve...

On Feb 19, 2009, at 8:26 PM, 任坤 wrote: > hi, Dear Evan Cheng: > > My cpu is i32 embeded CPU. I define pseudo register pair registers. > > In mytargetRegisterInfo.td: > def T0: RegisterWithSubRegs<"t0",[R0,R1]>; > ... > def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] > > In mytargetISelLowering.cpp: > I define i1, i8 , i16 and i32 are legal. > > 1. I still have problem. I save my...

...an LLVM Compiler Backend"), then all our files will be within LLVM sources and they will end up being tracked in the backend repository probably inducing painful merges each time we want to update the LLVM version we are tracking. Would it work using the sample project, creating a lib/Target/mytarget and go from there? Cheers, -- PMatos

On 18/8/23 15:39, Darren Tucker wrote: >> Host mytarget >> Hostname 172.16.1.2 >> ProxyJump user2 at bastion2 > I think you just need "HostKeyAlias mytarget" here. Ahh, in my scanning through the `ssh_config` manpage, I missed this, and change logs seem to indicate this feature has been around since at least...

Hi all, I'm getting this error: "Virtual register defs don't dominate all uses". It comes from llvm/lib/CodeGen/MachineVerifier.cpp:2138 I don't understand what it means. Does anyone know? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190416/f2eef252/attachment.html>

...looks as follows: /*4309*/ /*Scope*/ 12, /*->4322*/ /*4310*/ OPC_CheckOpcode, TARGET_VAL(MBPISD::RET_FLAG), /*4313*/ OPC_RecordNode, // #0 = 'retflag' chained node /*4314*/ OPC_CaptureGlueInput, /*4315*/ OPC_EmitMergeInputChains1_0, /*4316*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::RETL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0, 0/*#VTs*/, 0/*#Ops*/, // Src: (retflag) - Complexity = 3 // Dst: (RETL) /*4322*/ /*Scope*/ 11, /*->4334*/ /*4323*/ OPC_RecordNode, // #0 = $a /*4324*/ OPC_CheckType, MVT::i32, /*4326*/ OPC_Mo...