search for: bits

...MLX5_VIRTIO_NET_F_HOST_TSO4) - result |= BIT(VIRTIO_NET_F_HOST_TSO4); + result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO4); return result; } @@ -1459,15 +1459,15 @@ static u64 mlx5_vdpa_get_features(struct vdpa_device *vdev) dev_features = MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, device_features_bits_mask); ndev->mvdev.mlx_features = mlx_to_vritio_features(dev_features); if (MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, virtio_version_1_0)) - ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1); - ndev->mvdev.mlx_features |= BIT(VIRTIO_F_ACCESS_PLATFORM); + ndev->mvdev.mlx_featur...

...MLX5_VIRTIO_NET_F_HOST_TSO4) - result |= BIT(VIRTIO_NET_F_HOST_TSO4); + result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO4); return result; } @@ -1459,15 +1459,15 @@ static u64 mlx5_vdpa_get_features(struct vdpa_device *vdev) dev_features = MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, device_features_bits_mask); ndev->mvdev.mlx_features = mlx_to_vritio_features(dev_features); if (MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, virtio_version_1_0)) - ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1); - ndev->mvdev.mlx_features |= BIT(VIRTIO_F_ACCESS_PLATFORM); + ndev->mvdev.mlx_featur...

> I did some local testing and it seems that you are using a curve that is not acceptable for openssl as a server key. > > I tested with openssl s_server -cert ec-cert.pem -key ec-key.pem -port 5555 > > using cert generated with brainpool. Everything works if I use prime256v1 or secp521r1. This is a limitation in OpenSSL and not something we can really do anything about. > >

...k. I completely agree with you that we should be able to pass a hugepage as a single chunk. Also we shouldn't assume that host and guest have the same page size. I think we can come up with a scheme that actually lets us encode that into a 64-bit word, something like this: bit 0 clear => bits 1-11 encode a page count, bits 12-63 encode a PFN, page size 4k. bit 0 set, bit 1 clear => bits 2-12 encode a page count, bits 13-63 encode a PFN, page size 8k bits 0+1 set, bit 2 clear => bits 3-13 for page count, bits 14-63 for PFN, page size 16k. bits 0-2 set, bit 3 clear => bits 4-14 f...

...iversity\ProgettoInterdisciplinare\speex-1.2rc1\speex-1.2rc1\symbian\WINSCW.make" LIBRARY VERBOSE=-s make -s -r -f "\S60\devices\S60_3rd_FP2_SDK_v1.1\EPOC32\BUILD\Users\Maurizio\University\ProgettoInterdisciplinare\speex-1.2rc1\speex-1.2rc1\symbian\SPEEX\WINSCW\SPEEX.WINSCW" LIBRARY bits.c ..\libspeex\bits.c:48: declaration syntax error ..\libspeex\bits.c:49: declaration syntax error ..\libspeex\bits.c:54: declaration syntax error ..\libspeex\bits.c:56: declaration syntax error ..\libspeex\bits.c:58: identifier 'speex_bits_reset(struct SpeexBits *)' redeclared ..\libspeex\b...

...mes large amounts of band width nor gets to little band width. I originally wanted to filter just ports 6660-6669 but quickly realized that the bit masking wouldn''t allow for a single rule to cover them, so I opted instead to filter ports 6656-66671 which would give me the use of all 4 bits in that range. For reference, 6656 = 0x1a00, 6671 = 0x1a0f. As such, I have the following rules in my setup: eth0 egress to the internet (eth0 is the external interface): tc filter add dev eth0 parent 1: protocol ip prio 0 u32 \ match ip protocol 6 0xff \ match u16 0x1a00 0x1a0f at 22 \...

...rhaps this is fixed? If so, do let me know. I agree that perhaps 32 bit float/pcm isn't entirely necessary when it comes to storing different qualities. But when wanting to preserve floating point audio, I would think it would be a nice feature. I believe 32 bit floats have a precision of 23 bits when the audio is +/- 1.0, so in theory that would mean that 24 bit would have more precision but less dynamic range (if the floating point range is outside of +/- 1.0). The conversion to 24 bit would be a problem in that case. Best regards, Josh Green On Thu, 2007-03-29 at 12:07 -0700, Brian...

I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register. So for a basic 'a = b + c' example, we get %0 = load i32, i32* @b, align 4, !tbaa !1 %1 = load i32,...

...H/L=DC/O=foo.bar/OU=mail/CN=Server foo.bar Mail IMAP > >>> issuer=/C=00/ST=CH/O=foo.bar/OU=Server/CN=IM Server foo.bar > >>> --- > >>> No client certificate CA names sent > >>> Peer signing digest: SHA512 > >>> Server Temp Key: X25519, 253 bits > >>> --- > >>> SSL handshake has read 2361 bytes and written 295 bytes > >>> Verification error: unable to verify the first certificate > >>> --- > >>> New, TLSv1.2, Cipher is ECDHE-RSA-AES256-GCM-SHA384 > >>> Server public ke...

...ns diff --git a/libswfdec/swfdec_tag.c b/libswfdec/swfdec_tag.c index a556e19..ef1db99 100644 --- a/libswfdec/swfdec_tag.c +++ b/libswfdec/swfdec_tag.c @@ -387,43 +387,56 @@ swfdec_button_append_content (SwfdecButt static int tag_func_define_button_2 (SwfdecSwfDecoder * s, guint tag) { - SwfdecBits *bits = &s->b; - int id; - int flags; - int offset; + SwfdecBits bits; + int id, reserved; + guint length; SwfdecButton *button; char *script_name; - id = swfdec_bits_get_u16 (bits); + id = swfdec_bits_get_u16 (&s->b); button = swfdec_swf_decoder_create_character (s...

...e\speex\symbian\ library winscw make -r -f "\Symbian\9.1\S60_3rd_MR\EPOC32\BUILD\Symbian\Carbide\workspace\speex\symbian\WINSCW.make" LIBRARY VERBOSE=-s User break, cancelled... make[1]: *** [\Symbian\9.1\S60_3rd_MR\EPOC32\BUILD\Symbian\Carbide\workspace\speex\symbian\SPEEX\WINSCW\UDEB\bits.o] Error 2 make: *** [LIBRARYSPEEX] Error 2 make -s -r -f "\Symbian\9.1\S60_3rd_MR\EPOC32\BUILD\Symbian\Carbide\workspace\speex\symbian\SPEEX\WINSCW\SPEEX.WINSCW" LIBRARY bits.c ..\libspeex\bits.c:48: declaration syntax error ..\libspeex\bits.c:49: declaration syntax error ..\libspeex\bi...

On Fri, Mar 10, 2017 at 07:37:28PM +0800, Wei Wang wrote: > On 03/09/2017 10:14 PM, Matthew Wilcox wrote: > > On Fri, Mar 03, 2017 at 01:40:28PM +0800, Wei Wang wrote: > > > From: Liang Li <liang.z.li at intel.com> > > > 1) allocating pages (6.5%) > > > 2) sending PFNs to host (68.3%) > > > 3) address translation (6.1%) > > > 4) madvise

On Fri, Mar 10, 2017 at 07:37:28PM +0800, Wei Wang wrote: > On 03/09/2017 10:14 PM, Matthew Wilcox wrote: > > On Fri, Mar 03, 2017 at 01:40:28PM +0800, Wei Wang wrote: > > > From: Liang Li <liang.z.li at intel.com> > > > 1) allocating pages (6.5%) > > > 2) sending PFNs to host (68.3%) > > > 3) address translation (6.1%) > > > 4) madvise

...result |= BIT(VIRTIO_NET_F_HOST_TSO4); > + result |= BIT_ULL(VIRTIO_NET_F_HOST_TSO4); > > return result; > } > @@ -1459,15 +1459,15 @@ static u64 mlx5_vdpa_get_features(struct vdpa_device *vdev) > dev_features = MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, device_features_bits_mask); > ndev->mvdev.mlx_features = mlx_to_vritio_features(dev_features); > if (MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, virtio_version_1_0)) > - ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1); > - ndev->mvdev.mlx_features |= BIT(VIRTIO_F_ACCESS_PLATFORM); > +...

...x byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize { bit hasOpSizePrefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class TB { bits<4> Prefix = 1; } class REP { bits<4> Prefix = 2; } class D8 { bits<4> Prefix = 3; } class D9 { bits<4> Prefix = 4; } class DA { bits<4> Prefix = 5; } class DB { bits<4> Prefix = 6; } class DC { bits<4> Prefix = 7; } class DD { bit...

...sctl machdep.cpu.brand_string machdep.cpu.brand_string: Intel(R) Core(TM) i5-2415M CPU @ 2.30GHz $ /usr/bin/openssl speed rsa [...] LibreSSL 2.2.7 built on: date not available options:bn(64,64) rc4(ptr,int) des(idx,cisc,16,int) aes(partial) blowfish(idx) compiler: information not available rsa 512 bits 0.000964s 0.000059s 1037.3 16987.1 rsa 1024 bits 0.006052s 0.000271s 165.2 3687.3 rsa 2048 bits 0.040528s 0.001145s 24.7 873.6 rsa 4096 bits 0.278889s 0.004272s 3.6 234.1 $ libressl-2.2.7/apps/openssl speed rsa [...] options:bn(64,64) rc4(16x,int) des(idx,cisc,16,int) aes(pa...

...extending the 8-bit to 16-bit? 2. If that is the case then how will 24 bit PCM sample work? Regards Amit On Thu, Jan 7, 2016 at 12:21 PM, Ralph Giles <giles at thaumas.net> wrote: > On 07/01/16 10:04 AM, Amit Ashara wrote: > > > opus_decoder_ctl(sOpusDec, OPUS_SET_LSB_DEPTH(ui32BitsPerSample)); > > OPUS_SET_LSB_DEPTH only affects the encoder. If you check the return > value here you should get OPUS_UNIMPLEMENTED. > > > output_samples = opus_decode(sOpusDec, (const unsigned char > > *)&pcRdBuf[0], len, opi16_out, (ui32SizeOfWrBuf/ui8ScaleFactor), 0);...

libswfdec/swfdec_bits.c | 81 +++++++++++++++++++++++++++++----------------- libswfdec/swfdec_bits.h | 1 libswfdec/swfdec_sprite.c | 6 --- libswfdec/swfdec_tag.c | 12 ------ 4 files changed, 55 insertions(+), 45 deletions(-) New commits: diff-tree 493905baa1c07054276adb078f086e7ca4acc26b (from pare...

config.status: linking AUTHORS to dlls/shell32/AUTHORS config.status: linking tools/winewrapper to wine config.status: executing include/stamp-h commands config.status: executing dlls/gdi32/enhmfdrv commands config.status: executing dlls/gdi32/mfdrv commands config.status: executing dlls/kernel32/nls commands config.status: executing dlls/user32/resources commands config.status: executing

...;s style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propose to change LLVM/clang by adding: + a metadata 'targetflags' in LLVM atomic IR to pass this target-specific memory model hint + one extra target flag in AtomicSDN...