Hi all,
i'm working atm on a backend for a processor architecture that is
capable of storing the carry flag of ADDC in an 1-bit register class. So
I tried to lower the ADDC instruction to generate two register values as
result. On the tablegen description of the instruction i came across the
tablegen restriction that only one output result of one instruction is
possible:
assert(NumResults <= 1 &&
"We only work with nodes with zero or one result so far!");
So my question is now how much work it would be to remove this
restriction in tablegen. What do I have to take into consideration?
Thanks,
Timo Stripf
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On May 13, 2009, at 7:22 AM, Stripf, Timo wrote:> Hi all, > > i’m working atm on a backend for a processor architecture that is > capable of storing the carry flag of ADDC in an 1-bit register > class. So I tried to lower the ADDC instruction to generate two > register values as result. On the tablegen description of the > instruction i came across the tablegen restriction that only one > output result of one instruction is possible: > > assert(NumResults <= 1 && > "We only work with nodes with zero or one result so far!"); > > So my question is now how much work it would be to remove this > restriction in tablegen. What do I have to take into consideration? >I don't know offhand, but this would be a very welcome improvement! -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090513/be35e999/attachment.html>
hc2428 at columbia.edu
2009-May-13 18:36 UTC
[LLVMdev] DataStructure Analysis ds-aa can not stop when passing mysqld
Quoting Chris Lattner <clattner at apple.com>:
Dear staff,
I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12
statically (compile all libraries statically to the executable) and
got the bc file, named it as mysqld.bc3.
I use the command to pass:
opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa
mysqld.bc3 -print-alias-sets -disable-output
However, I got a lot of "cast in ... " on output screen like
this:
cast in strxnmov
%13 = inttoptr i32 %10 to i8* ; <i8*> [#uses=1]
In addition, and pass can not stop for a long time, and the last
output is the "cast in ... " as above.
Thanks,
Heming
>
> On May 13, 2009, at 7:22 AM, Stripf, Timo wrote:
>
>> Hi all,
>>
>> i?m working atm on a backend for a processor architecture that is
>> capable of storing the carry flag of ADDC in an 1-bit register
>> class. So I tried to lower the ADDC instruction to generate two
>> register values as result. On the tablegen description of the
>> instruction i came across the tablegen restriction that only one
>> output result of one instruction is possible:
>>
>> assert(NumResults <= 1 &&
>> "We only work with nodes with zero or one result so
far!");
>>
>> So my question is now how much work it would be to remove this
>> restriction in tablegen. What do I have to take into consideration?
>>
>
> I don't know offhand, but this would be a very welcome improvement!
>
> -Chris
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