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...oring the carry flag of ADDC in an 1-bit register class. So I tried to lower the ADDC instruction to generate two register values as result. On the tablegen description of the instruction i came across the tablegen restriction that only one output result of one instruction is possible: assert(NumResults <= 1 && "We only work with nodes with zero or one result so far!"); So my question is now how much work it would be to remove this restriction in tablegen. What do I have to take into consideration? Thanks, Timo Stripf -------------- next part --------------...

...1-bit register > class. So I tried to lower the ADDC instruction to generate two > register values as result. On the tablegen description of the > instruction i came across the tablegen restriction that only one > output result of one instruction is possible: > > assert(NumResults <= 1 && > "We only work with nodes with zero or one result so far!"); > > So my question is now how much work it would be to remove this > restriction in tablegen. What do I have to take into consideration? > I don't know offhand, but this would b...

...oring the carry flag of ADDC in an 1-bit register class. So I tried to lower the ADDC instruction to generate two register values as result. On the tablegen description of the instruction i came across the tablegen restriction that only one output result of one instruction is possible: assert(NumResults <= 1 && "We only work with nodes with zero or one result so far!"); So my question is now how much work it would be to remove this restriction in tablegen. What do I have to take into consideration? Thanks, Timo Stripf -------------- next part --------------...

...hineNode assumes that when the number of outputs of a MachineSDNode is greater than the number of defs in the corresponding MCInstrDesc, the outputs in the difference will be placed into physical registers as opposed to virtual registers. The specific line in question is: bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; Where NumResults is the number of outputs in the MachineSDNode and NumDefs comes from the MCInstrDesc and ultimately the TableGen definition of the instruction. I do not know why this assumption is made or what code depends on it, but it is ov...

...t; the number of outputs of a MachineSDNode is greater than the number of defs > in the corresponding MCInstrDesc, the outputs in the difference will be > placed into physical registers as opposed to virtual registers. > > The specific line in question is: > bool HasPhysRegOuts = NumResults > NumDefs && > II.getImplicitDefs()!=nullptr; > > Where NumResults is the number of outputs in the MachineSDNode and NumDefs > comes from the MCInstrDesc and ultimately the TableGen definition of the > instruction. I do not know why this assumption is made or what code dep...

...ass. So I tried to lower the ADDC instruction to generate two >> register values as result. On the tablegen description of the >> instruction i came across the tablegen restriction that only one >> output result of one instruction is possible: >> >> assert(NumResults <= 1 && >> "We only work with nodes with zero or one result so far!"); >> >> So my question is now how much work it would be to remove this >> restriction in tablegen. What do I have to take into consideration? >> > > I don't...

...puts of a MachineSDNode is greater than the number of defs >> in the corresponding MCInstrDesc, the outputs in the difference will be >> placed into physical registers as opposed to virtual registers. >> >> The specific line in question is: >> bool HasPhysRegOuts = NumResults > NumDefs && >> II.getImplicitDefs()!=nullptr; >> >> Where NumResults is the number of outputs in the MachineSDNode and >> NumDefs comes from the MCInstrDesc and ultimately the TableGen definition >> of the instruction. I do not know why this assumption is m...

...ess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile - This profile describes the type requirements of a Selection // DAG node. class SDTypeProfile<int numresults, int numoperands, list<SDTypeConstraint> constraints> { int NumResults = numresults; int NumOperands = numoperands; list<SDTypeConstraint> Constraints = constraints; } // So: 2 results, 3 operands....

...I tried to lower the ADDC instruction to generate two >>> register values as result. On the tablegen description of the >>> instruction i came across the tablegen restriction that only one >>> output result of one instruction is possible: >>> >>>  assert(NumResults <= 1 && >>>         "We only work with nodes with zero or one result so far!"); >>> >>> So my question is now how much work it would be to remove this >>> restriction in tablegen. What do I have to take into consideration? >>> >&g...

...I tried to lower the ADDC instruction to generate two >>> register values as result. On the tablegen description of the >>> instruction i came across the tablegen restriction that only one >>> output result of one instruction is possible: >>> >>> assert(NumResults <= 1 && >>> "We only work with nodes with zero or one result so far!"); >>> >>> So my question is now how much work it would be to remove this >>> restriction in tablegen. What do I have to take into consideration? >>> >&g...

...in>) at /Users/jholewinski/projects/llvm/src/llvm/lib/TableGen/Main.cpp:117 #15 0x00000001002d0864 in main (argc=11, argv=0x7fff5fbff8f8) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/TableGen.cpp:181 The fault occurs in CodeGenDAGPatterns.cpp: 2781 for (unsigned i = 0; i != NumResults; ++i) 2782 ResultPattern->setType(i, Res0Node->getExtType(i)); Res0Node has only 1 type, but it is expected to have 2. Looking at the X86 back-end code, it looks like there do exist multi-output instructions, but they all use physical (implicit) registers for the second destination,...

...should be our goal. I just wasn’t sure that was entirely possible. I’ll try adding implicit defs in the way you’ve suggested, but I’m concerned that there may be code that relies on the TII for that kind of thing -- for instance, InstrEmitter::EmitMachineNode() does this: bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; where “NumDefs” comes from TII and “NumResults” comes from the node. Obviously we can fix that up as needed, but it seems like a weak point in the design. Perhaps it is still better than trying to maintain a duplicate set of opcodes though....

...ode is greater than the number of defs >>> in the corresponding MCInstrDesc, the outputs in the difference will be >>> placed into physical registers as opposed to virtual registers. >>> >>> The specific line in question is: >>> bool HasPhysRegOuts = NumResults > NumDefs && >>> II.getImplicitDefs()!=nullptr; >>> >>> Where NumResults is the number of outputs in the MachineSDNode and >>> NumDefs comes from the MCInstrDesc and ultimately the TableGen definition >>> of the instruction. I do not know why...

...ojects/llvm/src/llvm/lib/TableGen/Main.cpp:117 > #15 0x00000001002d0864 in main (argc=11, argv=0x7fff5fbff8f8) at > /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/TableGen.cpp:181 > > > The fault occurs in CodeGenDAGPatterns.cpp: > > 2781 for (unsigned i = 0; i != NumResults; ++i) > 2782 ResultPattern->setType(i, Res0Node->getExtType(i)); > > Res0Node has only 1 type, but it is expected to have 2. > > > Looking at the X86 back-end code, it looks like there do exist > multi-output instructions, but they all use physical (implicit) regist...

...d, difficult > to follow, error: "Assertion `New->getNumTypes() == 1"). > > masked_gather returns 2 values because: > // SDTypeProfile - This profile describes the type requirements of a Selection > // DAG node. > class SDTypeProfile<int numresults, int numoperands, > list<SDTypeConstraint> constraints> { > int NumResults = numresults; > int NumOperands = numoperands; > list<SDTypeConstraint> Constraints = constraints; > } > > // So:...

...projects/llvm/src/llvm/lib/TableGen/Main.cpp:117 > #15 0x00000001002d0864 in main (argc=11, argv=0x7fff5fbff8f8) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/TableGen.cpp:181 > > > The fault occurs in CodeGenDAGPatterns.cpp: > > 2781 for (unsigned i = 0; i != NumResults; ++i) > 2782 ResultPattern->setType(i, Res0Node->getExtType(i)); > > Res0Node has only 1 type, but it is expected to have 2. > > > Looking at the X86 back-end code, it looks like there do exist multi-output instructions, but they all use physical (implicit) register...

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure:

...ib/TableGen/Main.cpp:117 >> #15 0x00000001002d0864 in main (argc=11, argv=0x7fff5fbff8f8) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/TableGen.cpp:181 >> >> >> The fault occurs in CodeGenDAGPatterns.cpp: >> >> 2781 for (unsigned i = 0; i != NumResults; ++i) >> 2782 ResultPattern->setType(i, Res0Node->getExtType(i)); >> >> Res0Node has only 1 type, but it is expected to have 2. >> >> >> Looking at the X86 back-end code, it looks like there do exist multi-output instructions, but they all use phys...

Hi, I'm writing a ModulePass that needs critical edges split up. I have the statement AU.addRequiredID(BreakCriticalEdgesID); in my getAnalysisUsage() but the pass never gets executed. I guess I have to request pass execution for each function, but I can't get behind how to do that, since there is no analysis group for that kind of transformation. Thanks, Andi

...etVR is the one assigning the virtual register no? Though this code in CreateVirtualRegisters: const TargetRegisterClass *RC = TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); That returns GPRBaseRegs for RC, but it then decides to constrain it based on type: if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { const TargetRegisterClass *VTRC = TLI->getRegClassFor(Node->getSimpleValueType(i)); errs()<<"CVR VTRC: "<<VTRC->getID()<<"\n"; if (RC) VTRC = TRI->ge...