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...estriction in tablegen. What do I have to take into consideration? > I don't know offhand, but this would be a very welcome improvement! -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090513/be35e999/attachment.html>

Hi all, i'm working atm on a backend for a processor architecture that is capable of storing the carry flag of ADDC in an 1-bit register class. So I tried to lower the ADDC instruction to generate two register values as result. On the tablegen description of the instruction i came across the tablegen restriction that only one output result of one instruction is possible: