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...n the LLVM publication page. http://www.llvm.org/pubs/ The first paper describes an architecture description language and LLVM back-end generation out of an ADL. The second paper describes a cluster VLIW back-end for LLVM 2.9, just before this VLIW initiative started for LLVM. Kind regards, Timo Stripf Stripf, T.; Koenig, R.; Becker, J.; , "A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors," Embedded Computer Systems (SAMOS), 2011 International Conference on , vol., no., pp.157-164, 18-21 July 2011 doi: 10.1109/SAMOS.2011.6045457 URL: http://...

...8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str1, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0] ret i32 undef } On little endian machines the code works correct but on big endian %lhsv must be compared against 73 << 8. Kind regards Timo Stripf -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090811/9ec73875/attachment.html>

On Tue, Aug 11, 2009 at 1:13 AM, Stripf, Timo<Timo.Stripf at itiv.uni-karlsruhe.de> wrote: > On little endian machines the code works correct but on big endian %lhsv > must be compared against 73 << 8. If llvm-gcc thinks it's compiling for a little-endian target, the optimizers will assume the target is little-endi...

...: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] Im Auftrag von Eli Friedman Gesendet: Dienstag, 11. August 2009 10:27 An: LLVM Developers Mailing List Betreff: Re: [LLVMdev] Bug in optimization pass related to strcmp and bigendian back-ends On Tue, Aug 11, 2009 at 1:13 AM, Stripf, Timo<Timo.Stripf at itiv.uni-karlsruhe.de> wrote: > On little endian machines the code works correct but on big endian %lhsv > must be compared against 73 << 8. If llvm-gcc thinks it's compiling for a little-endian target, the optimizers will assume the target is little-endi...

...What is the best way to solve this problem? I take a look at the DAG Optimizer and for this OR operation it calls DAGCombiner::SimplifyBinOpWithSameOpcodeHands that folds (OP (aext x), (aext y)) -> (aext (OP x, y)). No check if the new operation is legal is performed. Kind regards Timo Stripf -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090823/272a6e32/attachment.html>

...submit a patch? That sounds nice. I'll try out the svn code tomorrow. I think it'll take some days to converted the back-end to the new code base. -Timo -----Ursprüngliche Nachricht----- Von: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Gesendet: Sonntag, 23. August 2009 19:13 An: Stripf, Timo Cc: LLVM Developers Mailing List Betreff: Re: [LLVMdev] Problems with DAG Combiner On 23/08/2009, at 18.42, Stripf, Timo wrote: > Hi all, > > i'm writing an back-end for a new research processor architecture > and have problems with the DAG Combiner. The processor archite...

On Oct 25, 2011, at 1:59 AM, Stripf, Timo wrote: > Hi all, > >> Ok, so in your proposal a bundle is just a special MachineInstr? That sounds good. How are the MachineInstr's embedded inside a bundle? How are the cumulative operands, implicit register defs and uses represented? > > I attached the packing and u...

...t be a natural prerogative to implement it certain way for such hypothetical contributor/submitter? Thanks. Sergei Larin -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Wednesday, October 26, 2011 2:08 PM To: Stripf, Timo Cc: LLVM Dev Subject: Re: [LLVMdev] VLIW Ports On Oct 25, 2011, at 1:59 AM, Stripf, Timo wrote: > Hi all, > >> Ok, so in your proposal a bundle is just a special MachineInstr? That sounds good. How are the MachineInstr's embedded inside a bundle? How are the cumulative ope...

On 24/08/2009, at 01.19, Stripf, Timo wrote: > > I had also a lot of problems to get the i1 operations working. E.g. > I had to override the getSetCCResultType to get is working and for > ADDE/ADDC the i1 target registers are hardcoded. What is your SetCCResultType now? Can you compile the CodeGen/Blackfin/basic...

...nstruction is possible: assert(NumResults <= 1 && "We only work with nodes with zero or one result so far!"); So my question is now how much work it would be to remove this restriction in tablegen. What do I have to take into consideration? Thanks, Timo Stripf -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090513/48e9ae71/attachment.html>

...her problem came up when I tried to promote constant i1 values to i32. It required a custom legalization but later the instruction selector found i1 constants. So I suspect that DAG combiner reintroduced i1 constants. I gave up and added a related instruction to the architecture. Kind regards Timo Stripf -----Ursprüngliche Nachricht----- Von: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Gesendet: Montag, 24. August 2009 07:11 An: Stripf, Timo Cc: LLVM Developers Mailing List Betreff: Re: [LLVMdev] Problems with DAG Combiner On 24/08/2009, at 01.19, Stripf, Timo wrote: > > I had also...

...he PACK instruction but not used for unpacking. Unpacking reconstructs them from the TargetDescriptionInfo. I took a look at the packing/unpacking solution of Evan and I think it is more elegant to use a derived class of MachineInstr for storing multiple instructions into one. Best regards, Timo Stripf -----Ursprüngliche Nachricht----- Von: Evan Cheng [mailto:evan.cheng at apple.com] Gesendet: Dienstag, 25. Oktober 2011 01:55 An: Carlos Sánchez de La Lama Cc: Stripf, Timo; LLVM Dev Betreff: Re: [LLVMdev] VLIW Ports On Oct 24, 2011, at 2:38 PM, Carlos Sánchez de La Lama wrote: > Hi Evan (a...

...ed for some of this to make to LLVM trunk is to have a backend that uses it (can some dev confirm this?). My backend is still on the works, I have only a synthetic MIPS-VLIW working backend, but that is not a real target. Is your code public, or plan to be? BR Carlos El 22/10/2011, a las 02:52, Stripf, Timo escribió: > Hi all, > > I worked the last 2 years on a LLVM back-end that supports clustered and non-clustered VLIW architectures. I also wrote a paper about it that is currently within the review process and is hopefully going to be accepted. Here is a small summary how I realized...

...; on output screen like this: cast in strxnmov %13 = inttoptr i32 %10 to i8* ; <i8*> [#uses=1] In addition, and pass can not stop for a long time, and the last output is the "cast in ... " as above. Thanks, Heming > > On May 13, 2009, at 7:22 AM, Stripf, Timo wrote: > >> Hi all, >> >> i?m working atm on a backend for a processor architecture that is >> capable of storing the carry flag of ADDC in an 1-bit register >> class. So I tried to lower the ADDC instruction to generate two >> register value...

...losophy in an elegant and powerful way. First step to healing is to recognize that we have an issue ;) Sergei -----Original Message----- From: Carlos Sánchez de La Lama [mailto:carlos.delalama at urjc.es] Sent: Tuesday, October 25, 2011 4:24 AM To: Sergei Larin Cc: 'Evan Cheng'; 'Stripf, Timo'; 'LLVM Dev' Subject: RE: [LLVMdev] VLIW Ports Hi Sergei, > What would you say to a some sort of a "global cycle" field/marker to > determine all instructions scheduled at a certain "global" cycle. That way > the "bundle"/packet/multiop c...

...and useful to non-VLIW architectures to convey pre-schedule information down flow. Sergei Larin -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Carlos Sánchez de La Lama Sent: Monday, October 24, 2011 4:38 PM To: Evan Cheng Cc: Stripf, Timo; LLVM Dev Subject: Re: [LLVMdev] VLIW Ports Hi Evan (and all), > I think any implementation that makes a "bundle" a different entity from MachineInstr is going to be difficult to use. All of the current backend passes will have to taught to know about bundles. The approach in...

...eused in the same "global cycle" as it is killed. Carlos > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Carlos Sánchez de La Lama > Sent: Monday, October 24, 2011 4:38 PM > To: Evan Cheng > Cc: Stripf, Timo; LLVM Dev > Subject: Re: [LLVMdev] VLIW Ports > > Hi Evan (and all), > > > I think any implementation that makes a "bundle" a different entity from > MachineInstr is going to be difficult to use. All of the current backend > passes will have to taught to kn...

...dencies between them. The key is to introduce a concept that can be used by an existing target today. Sounds like what you are proposing is not very far what I've described. Do you have patches ready for review? Evan > > BR > > Carlos > >> On Oct 21, 2011, at 4:52 PM, Stripf, Timo wrote: >> >>> Hi all, >>> >>> I worked the last 2 years on a LLVM back-end that supports clustered and non-clustered VLIW architectures. I also wrote a paper about it that is currently within the review process and is hopefully going to be accepted. Here is...

...gt; First step to healing is to recognize that we have an issue ;) > > Sergei > > -----Original Message----- > From: Carlos Sánchez de La Lama [mailto:carlos.delalama at urjc.es] > Sent: Tuesday, October 25, 2011 4:24 AM > To: Sergei Larin > Cc: 'Evan Cheng'; 'Stripf, Timo'; 'LLVM Dev' > Subject: RE: [LLVMdev] VLIW Ports > > Hi Sergei, > >> What would you say to a some sort of a "global cycle" field/marker to >> determine all instructions scheduled at a certain "global" cycle. That way >> the &quo...

...ed as a unit, something that is never broken up by MI passes such as branch folding. This is something that current targets can use to, for example, pre-schedule instructions. This can be useful for macro-fusing optimization. It can also be used for VLIW targets. Evan On Oct 21, 2011, at 4:52 PM, Stripf, Timo wrote: > Hi all, > > I worked the last 2 years on a LLVM back-end that supports clustered and non-clustered VLIW architectures. I also wrote a paper about it that is currently within the review process and is hopefully going to be accepted. Here is a small summary how I realized VL...