search for: strxnmov

...able) and got the bc file, named it as mysqld.bc3. I use the command to pass: opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa mysqld.bc3 -print-alias-sets -disable-output However, I got a lot of "cast in ... " on output screen like this: cast in strxnmov %13 = inttoptr i32 %10 to i8* ; <i8*> [#uses=1] In addition, and pass can not stop for a long time, and the last output is the "cast in ... " as above. Thanks, Heming > > On May 13, 2009, at 7:22 AM, Stripf, Timo wrote: > >> Hi all, >&...

...d it as mysqld.bc3. >     I use the command to pass: > > opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa > mysqld.bc3 -print-alias-sets -disable-output > >     However, I got a lot of "cast in ... " on output screen like this: > > cast in strxnmov >         %13 = inttoptr i32 %10 to i8*           ; <i8*> [#uses=1] > >     In addition, and pass can not stop for a long time, and the last > output is the "cast in ... " as above. inttoptr casts are very bad for alias analysis. DSA has some code in it these days to t...

...it as mysqld.bc3. > I use the command to pass: > > opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa > mysqld.bc3 -print-alias-sets -disable-output > > However, I got a lot of "cast in ... " on output screen like this: > > cast in strxnmov > %13 = inttoptr i32 %10 to i8* ; <i8*> [#uses=1] > > In addition, and pass can not stop for a long time, and the last > output is the "cast in ... " as above. > > Thanks, > Heming > > >> >> On May 13, 2009, at 7:22 AM,...

On May 13, 2009, at 7:22 AM, Stripf, Timo wrote: > Hi all, > > i’m working atm on a backend for a processor architecture that is > capable of storing the carry flag of ADDC in an 1-bit register > class. So I tried to lower the ADDC instruction to generate two > register values as result. On the tablegen description of the > instruction i came across the tablegen

Hi all, i'm working atm on a backend for a processor architecture that is capable of storing the carry flag of ADDC in an 1-bit register class. So I tried to lower the ADDC instruction to generate two register values as result. On the tablegen description of the instruction i came across the tablegen restriction that only one output result of one instruction is possible: