thr3ads.net - llvm dev - [LLVMdev] Store patterns accepting i32 only? [Sep 2008]

If this information is useful, please help other people find it:
Share via:

Villmow, Micah

2008-Sep-23 17:44 UTC

[LLVMdev] Store patterns accepting i32 only?

I'm trying to write a store pattern that accepts both i32 and f32,
however, when tablegen generates the code, it only generates the code
for i32 only.

 

def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; 

def MEM  : Operand<i32> {

    let PrintMethod = "printMemOperand";

    let MIOperandInfo = (ops GPR, GPR);

}

def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore,

    [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 

 

def global_store : PatFrag<(ops node:$val, node:$ptr), 

    (st node:$val, node:$ptr), [{

        return isGlobalStore(dyn_cast<StoreSDNode>(N));

    }]>;

def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val,
MEM:$ptr),

                        "mov g[$ptr], $val",

                        [(global_store GPR:$val, ADDR:$ptr)]>;

 

I want this same pattern to be able to accept all the types for val that
GPR is mapped to(i32, i64, f32, f64).

Is there any way I can modify this so that it do what I want?

 

Here is a snippet of the generated code with the items bolded that I
don't want generated:

if (Predicate_global_store(N.Val)) {

    SDValue N1 = N.getOperand(1);

    SDValue N2 = N.getOperand(2);

    SDValue CPTmp0;

    SDValue CPTmp1;

    if (SelectADDR(N, N2, CPTmp0, CPTmp1)) {

 

      // Pattern: (st:void GPR:i32:$val,
ADDR:i32:$ptr)<<P:Predicate_global_store>>

      // Emits: (GLOBALSTORE_i32:void GPR:i32:$val, ADDR:i32:$ptr)

      // Pattern complexity = 13  cost = 1  size = 0

      if (N1.Val->getValueType(0) == MVT::i32 &&

          N2.Val->getValueType(0) == MVT::i32) {

        return Emit_14(N, AMDIL::GLOBALSTORE_i32, CPTmp0, CPTmp1);

      }

}

 

Thanks,

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

4555 Great America Pkwy,

Santa Clara, CA. 95054

P: 408-572-6219

F: 408-572-6596

 

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20080923/9619612b/attachment.html>

Chris Lattner

2008-Sep-23 23:05 UTC

head link

[LLVMdev] Store patterns accepting i32 only?

On Sep 23, 2008, at 10:44 AM, Villmow, Micah wrote:
> I’m trying to write a store pattern that accepts both i32 and f32,  
> however, when tablegen generates the code, it only generates the  
> code for i32 only.
>
> def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
> def MEM  : Operand<i32> {
>     let PrintMethod = "printMemOperand";
>     let MIOperandInfo = (ops GPR, GPR);
> }
> def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore,
>     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
>
> def global_store : PatFrag<(ops node:$val, node:$ptr),
>     (st node:$val, node:$ptr), [{
>         return isGlobalStore(dyn_cast<StoreSDNode>(N));
>     }]>;
> def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val, MEM: 
> $ptr),
>                         "mov g[$ptr], $val",
>                         [(global_store GPR:$val, ADDR:$ptr)]>;
>
> I want this same pattern to be able to accept all the types for val  
> that GPR is mapped to(i32, i64, f32, f64).
> Is there any way I can modify this so that it do what I want?
You probably want to use a multipattern ("defm").  This allows a  
single "line" of TD file to expand into multiple 'def's.  Take
a look
at the X86 SSE instructions for some examples of this.  Also, the  
tblgen document has some info as well,

-Chris
>
> Here is a snippet of the generated code with the items bolded that I  
> don’t want generated:
> if (Predicate_global_store(N.Val)) {
>     SDValue N1 = N.getOperand(1);
>     SDValue N2 = N.getOperand(2);
>     SDValue CPTmp0;
>     SDValue CPTmp1;
>     if (SelectADDR(N, N2, CPTmp0, CPTmp1)) {
>
>       // Pattern: (st:void GPR:i32:$val,  
> ADDR:i32:$ptr)<<P:Predicate_global_store>>
>       // Emits: (GLOBALSTORE_i32:void GPR:i32:$val, ADDR:i32:$ptr)
>       // Pattern complexity = 13  cost = 1  size = 0
>       if (N1.Val->getValueType(0) == MVT::i32 &&
>           N2.Val->getValueType(0) == MVT::i32) {
>         return Emit_14(N, AMDIL::GLOBALSTORE_i32, CPTmp0, CPTmp1);
>       }
> }
>
> Thanks,
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20080923/559e9266/attachment.html>

Villmow, Micah

2008-Sep-24 16:22 UTC

head link

[LLVMdev] Store patterns accepting i32 only?

The problem with that is I still have to write multiple multipatterns,
and in this particular case, I want the pattern to match all types of
the GPR register class, not just a single one of that class per
sub-pattern. The GPR register class has 32bit and 64 bit scalars along
with 32, 64, and 128 bit vector types. So the number of patterns I would
have to write is very large even with a multipattern but the instruction
produces for all of these types is the exact same, "mov g[$ptr],
$val".

 

Any other ideas that might work before I get started with the
multipattern stuff?

 

Thanks,

Micah

 

________________________________

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Chris Lattner
Sent: Tuesday, September 23, 2008 4:05 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Store patterns accepting i32 only?

 

 

On Sep 23, 2008, at 10:44 AM, Villmow, Micah wrote:





I'm trying to write a store pattern that accepts both i32 and f32,
however, when tablegen generates the code, it only generates the code
for i32 only.

 

def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;

def MEM  : Operand<i32> {

    let PrintMethod = "printMemOperand";

    let MIOperandInfo = (ops GPR, GPR);

}

def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore,

    [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;

 

def global_store : PatFrag<(ops node:$val, node:$ptr),

    (st node:$val, node:$ptr), [{

        return isGlobalStore(dyn_cast<StoreSDNode>(N));

    }]>;

def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val,
MEM:$ptr),

                        "mov g[$ptr], $val",

                        [(global_store GPR:$val, ADDR:$ptr)]>;

 

I want this same pattern to be able to accept all the types for val that
GPR is mapped to(i32, i64, f32, f64).

Is there any way I can modify this so that it do what I want?

 

You probably want to use a multipattern ("defm").  This allows a
single
"line" of TD file to expand into multiple 'def's.  Take a look
at the
X86 SSE instructions for some examples of this.  Also, the tblgen
document has some info as well,

 

-Chris





 

Here is a snippet of the generated code with the items bolded that I
don't want generated:

if (Predicate_global_store(N.Val)) {

    SDValue N1 = N.getOperand(1);

    SDValue N2 = N.getOperand(2);

    SDValue CPTmp0;

    SDValue CPTmp1;

    if (SelectADDR(N, N2, CPTmp0, CPTmp1)) {

 

      // Pattern: (st:void GPR:i32:$val,
ADDR:i32:$ptr)<<P:Predicate_global_store>>

      // Emits: (GLOBALSTORE_i32:void GPR:i32:$val, ADDR:i32:$ptr)

      // Pattern complexity = 13  cost = 1  size = 0

      if (N1.Val->getValueType(0) == MVT::i32 &&

          N2.Val->getValueType(0) == MVT::i32) {

        return Emit_14(N, AMDIL::GLOBALSTORE_i32, CPTmp0, CPTmp1);

      }

}

 

Thanks,

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

4555 Great America Pkwy,

Santa Clara, CA. 95054

P: 408-572-6219

F: 408-572-6596

 

_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev



 

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20080924/f90bd544/attachment.html>

Seemingly Similar Threads

Search for more reasonably related threads

llvm dev - Sep 2008 - [LLVMdev] Store patterns accepting i32 only?

[LLVMdev] Store patterns accepting i32 only?

[LLVMdev] Store patterns accepting i32 only?

[LLVMdev] Store patterns accepting i32 only?

Seemingly Similar Threads