Displaying 3 results from an estimated 3 matches for "cptmp0".
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cptmp1
2008 Sep 23
2
[LLVMdev] Store patterns accepting i32 only?
...i64, f32, f64).
Is there any way I can modify this so that it do what I want?
Here is a snippet of the generated code with the items bolded that I
don't want generated:
if (Predicate_global_store(N.Val)) {
SDValue N1 = N.getOperand(1);
SDValue N2 = N.getOperand(2);
SDValue CPTmp0;
SDValue CPTmp1;
if (SelectADDR(N, N2, CPTmp0, CPTmp1)) {
// Pattern: (st:void GPR:i32:$val,
ADDR:i32:$ptr)<<P:Predicate_global_store>>
// Emits: (GLOBALSTORE_i32:void GPR:i32:$val, ADDR:i32:$ptr)
// Pattern complexity = 13 cost = 1 size = 0
if...
2009 Jan 14
2
[LLVMdev] Use two ComplexPatterns (possible bug of TableGen?)
...(ins regsw:$src0, regsw:$src1),
"mul $dst, $src0, $src1",
[(set VR128:$dst, (mul regsw:$src0, regsw:$src1))]>;
The code generate by TableGen is:
SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
SDValue N0 = N.getOperand(0);
SDValue CPTmp0;
SDValue CPTmp1;
if (SelectRegsw(N, N0, CPTmp0, CPTmp1)) {
SDValue N1 = N.getOperand(1);
SDValue CPTmp0;
SDValue CPTmp1;
if (SelectRegsw(N, N1, CPTmp0, CPTmp1)) {
return Emit_1(N, FooVS::MUL_1, MVT::v4i32, CPTmp0, CPTmp1);
}
}
2008 Sep 23
0
[LLVMdev] Store patterns accepting i32 only?
...the
tblgen document has some info as well,
-Chris
>
> Here is a snippet of the generated code with the items bolded that I
> don’t want generated:
> if (Predicate_global_store(N.Val)) {
> SDValue N1 = N.getOperand(1);
> SDValue N2 = N.getOperand(2);
> SDValue CPTmp0;
> SDValue CPTmp1;
> if (SelectADDR(N, N2, CPTmp0, CPTmp1)) {
>
> // Pattern: (st:void GPR:i32:$val,
> ADDR:i32:$ptr)<<P:Predicate_global_store>>
> // Emits: (GLOBALSTORE_i32:void GPR:i32:$val, ADDR:i32:$ptr)
> // Pattern complexity = 13...