On Jun 11, 2007, at 7:22 PM, Evan Cheng wrote:> > On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote: > >> >> What's the best way to get an SDNode through to DAG scheduling >> without getting mangled during Lowering/ISel? > > What do you mean by "mangled"? Please clarify.My mangled I mean the nodes shouldn't be isel'ed into anything else because they need to survive through to scheduling. Is there a preferred means of having those nodes skipped during selection and lowering?>> >> When should subregs be flattened to actual registers: AsmPrinter? >> Somewhere in LiveIntervals, during RegAlloc? > > You mean turning part of a larger physical register into a sub- > register?Yes.> I would think LiveIntervals or else copy coalescing might > not work right.Ok. Can you give me some hints as to starting points in LiveIntervals? -- Chris> > Evan > >> >> Is there are common API used to turn vregs into physregs that could >> be changed to flatten any subregs in a central location? >> -- >> Christopher Lamb >> >> >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev-- Christopher Lamb -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070612/7e9e7e7e/attachment.html>
On Tue, 12 Jun 2007, Christopher Lamb wrote:>> > What's the best way to get an SDNode through to DAG scheduling >> > without getting mangled during Lowering/ISel? >> >> What do you mean by "mangled"? Please clarify. > > My mangled I mean the nodes shouldn't be isel'ed into anything else because > they need to survive through to scheduling. Is there a preferred means of > having those nodes skipped during selection and lowering?You'll have to teach legalize and isel about these nodes, just like they know about ISD::Register nodes. subregs will be a new first-class node type that all of the dag stuff will have to know about (at least to pass them through).>> > When should subregs be flattened to actual registers: AsmPrinter? >> > Somewhere in LiveIntervals, during RegAlloc?This should definitely be done during regalloc. -Chris -- http://nondot.org/sabre/ http://llvm.org/
On Jun 12, 2007, at 10:53 AM, Chris Lattner wrote:> On Tue, 12 Jun 2007, Christopher Lamb wrote: >>>> What's the best way to get an SDNode through to DAG scheduling >>>> without getting mangled during Lowering/ISel? >>> >>> What do you mean by "mangled"? Please clarify. >> >> My mangled I mean the nodes shouldn't be isel'ed into anything >> else because >> they need to survive through to scheduling. Is there a preferred >> means of >> having those nodes skipped during selection and lowering? > > You'll have to teach legalize and isel about these nodes, just like > they > know about ISD::Register nodes. subregs will be a new first-class > node > type that all of the dag stuff will have to know about (at least to > pass > them through).Great! Found the spot to do that.> >>>> When should subregs be flattened to actual registers: AsmPrinter? >>>> Somewhere in LiveIntervals, during RegAlloc? > > This should definitely be done during regalloc.It seems that LiveIntervals will need to be taught about the new form of virtual registers. Hrm. I'm going to try to break this work up as much as possible. Also, do you see any problems with using the following class for vregs? It makes it possible to not have to go through and update every call site for a large number of functions. class vreg : public std::pair<unsigned,unsigned> { public: vreg(unsigned f) : std::pair<unsigned,unsigned>(f, 0) {} }; If this definition is OK, where should it live? It's needed all over the place... -- Christopher Lamb -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070612/5f81b159/attachment.html>