search for: pr1350

On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote: > > What's the best way to get an SDNode through to DAG scheduling > without getting mangled during Lowering/ISel? What do you mean by "mangled"? Please clarify. > > When should subregs be flattened to actual registers: AsmPrinter? > Somewhere in LiveIntervals, during RegAlloc? You mean turning part of a

On Tue, 12 Jun 2007, Christopher Lamb wrote: >> > What's the best way to get an SDNode through to DAG scheduling >> > without getting mangled during Lowering/ISel? >> >> What do you mean by "mangled"? Please clarify. > > My mangled I mean the nodes shouldn't be isel'ed into anything else because > they need to survive through to

On Jun 13, 2007, at 10:50 AM, Chris Lattner wrote: > On Tue, 12 Jun 2007, Christopher Lamb wrote: >>>>>> When should subregs be flattened to actual registers: >>>>>> AsmPrinter? >>>>>> Somewhere in LiveIntervals, during RegAlloc? >>> >>> This should definitely be done during regalloc. >> >> It seems that

What's the best way to get an SDNode through to DAG scheduling without getting mangled during Lowering/ISel? When should subregs be flattened to actual registers: AsmPrinter? Somewhere in LiveIntervals, during RegAlloc? Is there are common API used to turn vregs into physregs that could be changed to flatten any subregs in a central location? -- Christopher Lamb

On Tue, 12 Jun 2007, Christopher Lamb wrote: >> > > > When should subregs be flattened to actual registers: AsmPrinter? >> > > > Somewhere in LiveIntervals, during RegAlloc? >> >> This should definitely be done during regalloc. > > It seems that LiveIntervals will need to be taught about the new form of > virtual registers. Hrm. I'm

On Jun 11, 2007, at 7:22 PM, Evan Cheng wrote: > > On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote: > >> >> What's the best way to get an SDNode through to DAG scheduling >> without getting mangled during Lowering/ISel? > > What do you mean by "mangled"? Please clarify. My mangled I mean the nodes shouldn't be isel'ed into anything else

On Jun 12, 2007, at 10:53 AM, Chris Lattner wrote: > On Tue, 12 Jun 2007, Christopher Lamb wrote: >>>> What's the best way to get an SDNode through to DAG scheduling >>>> without getting mangled during Lowering/ISel? >>> >>> What do you mean by "mangled"? Please clarify. >> >> My mangled I mean the nodes shouldn't be

hi, the architecture that we are compiling for has a special vector shuffle instruction, which writes two successive registers (Rn and Rn+1). i have defined intrinsics to generate the instruction, and a special register class for the register pairs. in addition i have two EXTRACT operations which allow to access either the first or second subregister of a pair (using moves). the pair register

...s across blocks to reduce register pressure. 24. Evan added support for tracking physreg sub-registers and super-registers in the code generator, as well as extensive register allocator changes to track them. 25. Nate contributed initial support for virtreg sub-registers. See PR1350 for more information. Target-Specific Code Generator Enhancements: 26. Nicolas Geoffray contributed support for the Linux/ppc ABI, and the linux/ppc JIT is fully functional now. llvm-gcc and static compilation are not fully supported yet though. 27. Bill contributed support for the X...

...expressions across blocks to reduce register pressure. x. Evan added support for tracking physreg sub-registers and super- registers in the code generator, as well as extensive register allocator changes to track them. x. Nate contributed initial support for virtreg sub-registers. See PR1350 for more information. Target-Specific Code Generator Enhancements: x. Nicolas Geoffray contributed support for the Linux/ppc ABI, and the linux/ppc JIT is fully functional now. llvm-gcc and static compilation are not fully supported yet though. x. Bill contributed support for the X86 M...